High-performance sequence estimation system and method of operation
An electronic receiver comprises sequence estimation circuitry operable to implement a sequence estimation algorithm. In the sequence estimation algorithm, each of a plurality of possible current states of the signal may have associated with it a respective N c possible prior states and a respective M state extensions, where N c and M are integers greater than 1. Each iteration of the sequence estimation algorithm may comprise extending each of the plurality of possible current states of the signal by its respective N c possible prior states and its respective M state extensions to generate a respective N c ×M extended states for each of the plurality of possible current states. Each iteration of the sequence estimation algorithm may comprise, for each of the plurality of possible current states of the signal, selecting M of the respective N c ×M extended states to be state extensions for a next iteration of the sequence estimation algorithm.
1. A system comprising:
an electronic receiver comprising:
front-end circuitry operable to receive a signal over a communication channel, wherein said received signal is a result of a sequence of symbols being transmitted by a transmitter; and
sequence estimation circuitry operable to implement a sequence estimation algorithm in which:
each of a plurality of possible current states of said received signal has associated with it a respective N c possible prior states and a respective M state extensions, where N c and M are integers greater than 1;
for each iteration of said sequence estimation algorithm:
each of said plurality of possible current states of said received signal is extended by its respective N c possible prior states and its respective M state extensions to generate a respective N c ×M extended states for each of said plurality of possible current states; and
for each of said plurality of possible current states of said received signal, M of said respective N c ×M extended states are selected to be state extensions for a next iteration of said sequence estimation algorithm.
2. The system of claim 1 , wherein how many states are in said plurality of possible current states is less than a full Viterbi state count.
3. The system of claim 1 , wherein each of said plurality of possible current states corresponds to a sequence of cosets of a symbol constellation used to generate said sequence of symbols.
4. The system of claim 3 , wherein a coset of said sequence of cosets corresponds to one or more least significant bits of a symbol.
5. The system of claim 4 , wherein said sequence estimation circuitry is operable to, after determination of said least significant bits based on a plurality of metrics, determine most significant bits of said symbol using slicing.
6. The system of claim 4 , wherein said sequence estimation circuitry is operable to, after determination of said least significant bits based on a plurality of metrics, determine most significant bits of said symbol using a second iteration of said sequence estimation algorithm in which said determined least significant bits are held fixed.
7. The system of claim 4 , wherein said sequence estimation circuitry is operable to determine a first one or more most significant bits of said symbol using slicing and a second one or more most significant bits of said symbol using a second iteration of said sequence estimation algorithm in which previously determined least significant bits are held fixed.
8. The system of claim 1 , wherein said state extensions correspond to prior state information that is older than prior state information represented by said N c possible prior states.
9. The system of claim 1 , wherein said sequence estimation circuitry is operable to sort said N c ×M extended states for each of said plurality of possible current states.
10. A method comprising:
in an electronic receiver:
receiving, via front-end circuitry of said electronic receiver, a signal over a communication channel, wherein said received signal is a result of a sequence of symbols being transmitted by a transmitter; and
demodulating, in sequence estimation circuitry of said electronic receiver, said received signal using a sequence estimation algorithm in which:
each of a plurality of possible current states of said received signal has associated with it a respective N c possible prior states and a respective M state extensions, where N c and M are integers greater than 1; and
each iteration comprises:
extending each of said plurality of possible current states of said received signal by its respective N c possible prior states and its respective M state extensions to generate a respective N c ×M extended states for each of said plurality of possible current states; and
for each of said plurality of possible current states of said received signal, selecting M of said respective N c ×M extended states to be state extensions for a next iteration of said sequence estimation algorithm.
11. The method of claim 10 , wherein how many states are in said plurality of possible current states is less than a full Viterbi state count.
12. The system of claim 10 , wherein each of said plurality of possible current states corresponds to a sequence of cosets of a symbol constellation used to generate said sequence of symbols.
13. The system of claim 12 , wherein a coset of said sequence of cosets corresponds to one or more least significant bits of a symbol.
14. The system of claim 13 , comprising:
determining, by said sequence estimation circuitry, said least significant bits based on a plurality of metrics; and
after said determining said least significant bits, determining, by said sequence estimation circuitry, most significant bits of said symbol using slicing.
15. The system of claim 13 , comprising:
determining, by said sequence estimation circuitry, said least significant bits based on a plurality of metrics; and
after said determining said least significant bits, determining, by said sequence estimation circuitry, most significant bits of said symbol using a second iteration of said sequence estimation algorithm in which said determined least significant bits are held fixed.
16. The system of claim 13 , comprising determining, by said sequence estimation circuit, a first one or more most significant bits of said symbol using slicing and a second one or more most significant bits of said symbol using a second iteration of said sequence estimation algorithm in which previously determined least significant bits are held fixed.
17. The system of claim 10 , wherein said state extensions correspond to prior state information that is older than prior state information represented by said N c possible prior states.
18. The system of claim 10 , comprising sorting, by said sequence estimation circuitry, said N c ×M extended states for each of said plurality of possible current states.
19. A system comprising:
an electronic receiver comprising:
front-end circuitry operable to receive a signal over a communication channel, wherein said received signal is a result of a sequence of symbols being transmitted by a transmitter; and
sequence estimation circuitry operable to implement a sequence estimation algorithm in which:
at symbol time n−1, a particular possible state of said received signal is extended by N c possible prior states for said particular possible state, resulting in N c extended states;
at symbol time n−1, each of said N c extended states is extended by M first state extension tails, resulting in N c ×M first extended states with tails;
at symbol time n−1, M of said N c ×M extended states with tails are selected as second state extension tails for said particular possible state; and
at symbol time n, said M second state extension tails is used for generating second extended states with tails.