Controlling the latchup effect
View Patent ↗A method includes varying spacing between at least one of a source region or a drain region and a well contact region to create a group of configurations. The method further includes determining an effect of latchup on each configuration.
1. A latchup monitor comprising:
a first complementary metal oxide semiconductor (CMOS) circuit that includes a first source region, a first drain region, and a first well contact region; and
a second CMOS circuit that includes a second source region, a second drain region, and a second well contact region,
the latchup monitor to analyze an effect of latchup on:
the first CMOS circuit with respect to a size of the first source region and the first drain region, and
the second CMOS circuit with respect to a size of the second source region and the second drain region,
a CMOS circuit without latchup and with a source region and a drain region of a maximum size being identified based on analyzing the effect of latchup.
2. The latchup monitor of claim 1 , where a length of the first source region and the first drain region exceeds a length of the first well contact region, and
where a length of the second source region and the second drain region exceeds a length of the second well contact region.
3. The latchup monitor of claim 2 , where the length of the first well contact region is substantially equal to the length of the second well contact region.
4. The latchup monitor of claim 1 , where a width of the first source region and the first drain region exceeds a width of the first well contact region, and
where a width of the second source region and the second drain region exceeds a width of the second well contact region.
5. The latchup monitor of claim 4 , where a length of the first source region and the first drain region exceeds a length of the first well contact region, and
a length of the second source region and the second drain region exceeds a length of the second well contact region.
6. The latchup monitor of claim 4 , where a length of the first source region and the first drain region is substantially equal to a length of the first well contact region, and
where a length of the second source region and the second drain region is substantially equal to a length of the second well contact region.
7. The latchup monitor of claim 1 , where the latchup monitor is included in a semiconductor device.
8. A semiconductor device comprising:
a latchup monitor comprising:
a first complementary metal oxide semiconductor (CMOS) circuit that includes a first source region and a first drain region; and
a second CMOS circuit that includes a second source region and a second drain region,
the latchup monitor to analyze an effect of latchup on:
the first CMOS circuit with respect to a size of the first source region and the first drain region, and
the second CMOS circuit with respect to a size of the second source region and the second drain region,
a CMOS circuit without latchup and with a source region and a drain region of a maximum size being identified based on analyzing the effect of latchup.
9. The semiconductor device of claim 8 , where the CMOS circuit corresponds to a CMOS circuit without latchup and with at least one of:
a source region and a drain region of a maximum length, or
a source region and a drain region of a maximum width.
10. The semiconductor device of claim 8 , where a width of the first source region and the first drain region exceeds a width of a first well contact region of the first CMOS circuit, and
where a width of the second source region and the second drain region exceeds a width of a second well contact region of the second CMOS circuit.
11. The semiconductor device of claim 10 , where a length of the first source region and the first drain region exceeds a length of the first well contact region, and
where a length of the second source region and the second drain region exceeds a length of the second well contact region.
12. The semiconductor device of claim 10 , where a length of the first source region and the first drain region is substantially equal to a length of the first well contact region, and
where a length of the second source region and the second drain region is substantially equal to a length of the second well contact region.
13. The semiconductor device of claim 8 , where a length of the first source region and the first drain region exceeds a length of a first well contact region of the first CMOS circuit, and
where a length of the second source region and the second drain region exceeds a length of a second well contact region of the second CMOS circuit.
14. The semiconductor device of claim 13 , where a width of the first source region and the first drain region is substantially equal to a width of the first well contact region, and
where a width of the second source region and the second drain region is substantially equal to a width of the second well contact region.
15. The semiconductor device of claim 13 , where the length of the first well contact region is substantially equal to the length of the second well contact region.
16. A latchup monitor comprising
a first complementary metal oxide semiconductor (CMOS) circuit that includes a first source region, a first drain region, and a first well contact region; and
a second CMOS circuit that includes a second source region, a second drain region, and a second well contact region,
the latchup monitor to:
analyze an effect of latchup on:
the first CMOS circuit with respect to a size of the first source region and the first drain region or with respect to a size of the first well contact region, and
the second CMOS circuit with respect to a size of the second source region and the second drain region or with respect to a size of the second well contact region, and
determine, based on analyzing the effect of latchup, a CMOS circuit without latchup and with:
a well contact region of a minimum size, or
a source region and a drain region of a maximum size.
17. The latchup monitor of claim 16 , where the CMOS circuit corresponds to a CMOS circuit without latchup and with at least one of:
a source region and a drain region of a maximum length, or
a source region and a drain region of a maximum width.
18. The latchup monitor of claim 17 , where the size of the first well contact region and the size of the second well contact region are fixed.
19. The latchup monitor of claim 16 , where the CMOS circuit corresponds to a CMOS circuit without latchup and with a well contact region of a minimum length.
20. The latchup monitor of claim 19 , where a length of the first source region and the first drain region is fixed, and
where a length of the second source region and the second drain region is fixed.