Fault tolerant link width maximization in a data bus
View Patent ↗Embodiments of systems and methods for fault tolerant link width maximization in a data bus are described. Embodiments of methods may include checking a data bus connection to determine if a degraded lane exists on the data bus, determining a first set of one or more lanes that contain the degraded lane, and assigning a second set of lanes for operation, wherein the second set of lanes does not contain the degraded lane.
1. A method comprising:
checking a data bus connection to determine if a degraded lane exists on the data bus;
determining a first set of one or more lanes that contain the degraded lane;
assigning a second set of lanes for operation, wherein the second set of lanes does not contain the degraded lane; and
logically dividing the second set of lanes into a plurality of groups of lanes and assigning the plurality of groups of lanes in logical connections to a plurality of hosts respectively.
2. The method of claim 1 , wherein checking the data bus connection includes communicating out of band with a data bus driver to determine whether any of the lanes are degraded.
3. The method of claim 1 , wherein determining a first set of one or more lanes that contain the degraded lane comprises bifurcating the data bus into a plurality of groups of lanes and checking the connectivity of each group of lanes to determine whether each group has full connectivity.
4. The method of claim 3 , further comprising further bifurcating the first set of one or more lanes to isolate a set of one or more degraded lanes.
5. The method of claim 3 , further comprising bifurcating the lanes down to a fixed width smaller than the total bus width.
6. The method of claim 1 , further comprising generating a log of the first set of lanes that contain the degraded lane.
7. The method of claim 1 , further comprising synchronizing lane configurations at both endpoints of the data bus.
8. A system comprising:
a data bus having a plurality of lanes, each lane comprising a differential pair of conductors; and
a data bus controller coupled to the data bus, the data bus controller configured to:
check a data bus connection to determine if a degraded lane exists on the data bus;
determine a first set of one or more lanes that contain the degraded lane;
assign a second set of lanes for operation, wherein the second set of lanes does not contain the degraded lane; and
logically divide the second set of lanes into a plurality of groups of lanes, and assign the plurality of groups of lanes in logical connections to a plurality of hosts respectively.
9. The system of claim 8 , wherein the data bus controller is configured to check the data bus connection by communicating out of band with a data bus driver to determine whether any of the lanes are degraded.
10. The system of claim 8 , wherein the data bus controller is further configured to bifurcate the data bus into a plurality of groups of lanes and checking connectivity of each group of lanes to determine whether each group has full connectivity.
11. The system of claim 10 , wherein the data bus controller is further configured to bifurcate the first set of one or more lanes to isolate a set of one or more degraded lanes.
12. The system of claim 10 , wherein the data bus controller is further configured to bifurcate the lanes down to a fixed width smaller than the total bus width.
13. The system of claim 8 , wherein the data bus controller is further configured to generate a log of the first set of lanes that contain the degraded lane.
14. The system of claim 8 , wherein the data bus controller is further configured to synchronize lane configurations at both endpoints of the data bus.
15. A tangible non-transitory medium comprising machine executable instructions that, when executed by a machine, cause the machine to perform operations comprising:
checking a data bus connection to determine if a degraded lane exists on the data bus;
determining a first set of one or more lanes that contain the degraded lane;
assigning a second set of lanes for operation, wherein the second set of lanes does not contain the degraded lane; and
logically dividing the second set of lanes into a plurality of groups of lanes, and assigning the plurality of groups of lanes in logical connections to a plurality of hosts respectively.
16. The tangible medium of claim 15 , wherein checking the data bus connection includes communicating out of band with a data bus driver to determine whether any of the lanes are degraded.
17. The tangible medium of claim 15 , wherein the data bus controller is further configured to bifurcate the data bus into a plurality of groups of lanes and checking connectivity of each group of lanes to determine whether each group has full connectivity.
18. The tangible medium of claim 17 , further comprising further bifurcating the first set of one or more lanes to isolate a set of one or more degraded lanes.
19. The tangible medium of claim 17 , further comprising bifurcating the lanes down to a fixed width smaller than the total bus width.
20. The tangible medium of claim 15 , further comprising generating a log of the first set of lanes that contain the degraded lane.