Method for estimating the diffusion length of metallic species within a three-dimensional integrated structure, and corresponding three-dimensional integrated structure
View Patent ↗A three-dimensional integrated structure may include two assembled integrated circuits respectively including two metallic lines, and at least two cavities passing through one of the integrated circuits and opening onto two locations respectively in electrical contact with the two metallic lines. The cavities may be sized to place a measuring apparatus at the bottom of the cavities, and in electrical contact with the two locations.
1. An integrated structure comprising:
a pair of integrated circuits (ICs) having upper faces joined together to define an interface therebetween and with each IC including a respective one of a pair of metallic lines at the interface, the pair of metallic lines being laterally spaced apart to permit diffusion therebetween, a first IC of said pair of ICs having a plurality of cavities extending from a surface of said first IC and passing therethrough and opening onto respective electrical contact locations in electrical contact with said pair of metallic lines, one of the plurality of cavities extending through the interface to a second IC of said pair of ICs.
2. The integrated structure according to claim 1 , wherein the plurality of cavities each has a height greater than 5 microns.
3. The integrated structure according to claim 1 , wherein the plurality of cavities each has a height less than 15 microns.
4. The integrated structure according to claim 1 , wherein the first IC has a thickness less than a thickness of the second IC.
5. The integrated structure according to claim 1 , wherein the plurality of cavities each has a plurality of walls extending from a bottom; and further comprising a conductive layer at the bottom and on said plurality of walls.
6. The integrated structure according to claim 1 , wherein said pair of ICs comprises a pair of assembled ICs.
7. The integrated structure according to claim 1 , wherein the plurality of cavities each has a width greater than 80 microns.
8. An integrated structure comprising:
a pair of integrated circuits (ICs) having upper faces joined together to define an interface therebetween and with each IC including a respective one of a pair of conductive lines at the interface, the pair of conductive lines being laterally spaced apart to permit diffusion therebetween, a first IC of said pair of ICs having a plurality of cavities extending from a surface of said first IC and passing therethrough and opening onto respective electrical contact locations in electrical contact with said pair of conductive lines, one of the plurality of cavities extending through the interface to a second IC of said pair of ICs;
the plurality of cavities each having a width greater than 80 microns and a height greater than 5 microns.
9. The integrated structure according to claim 8 , wherein the plurality of cavities each have a height less than 15 microns.
10. The integrated structure according to claim 8 , wherein the first IC has a thickness less than a thickness of the second IC.
11. The integrated structure according to claim 8 , wherein the plurality of cavities each has a plurality of walls extending from a bottom; and further comprising a conductive layer at the bottom and on said plurality of walls.
12. The integrated structure according to claim 8 , wherein said pair of ICs comprises a pair of assembled ICs.
13. An integrated structure comprising:
a pair of integrated circuits (ICs) having upper faces joined together to define an interface therebetween and with each IC including a respective one of a pair of metallic lines at the interface, the pair of metallic lines being laterally spaced apart to permit diffusion therebetween, a first IC of said pair of ICs having a plurality of cavities extending from a surface of said first IC and passing therethrough and opening onto respective electrical contact locations in electrical contact with said pair of metallic lines, one of the plurality of cavities extending through the interface to a second IC of said pair of ICs;
the plurality of cavities each having a width greater than 80 microns, and a height greater than 5 microns and less than 15 microns.
14. The integrated structure according to claim 13 , wherein the first IC has a thickness less than a thickness of the second IC.
15. The integrated structure according to claim 13 , wherein the plurality of cavities each has a plurality of walls extending from a bottom; and further comprising a conductive layer at the bottom and on said plurality of walls.
16. The integrated structure according to claim 13 , wherein said pair of ICs comprises a pair of assembled ICs.