Semiconductor device

1. A semiconductor device comprising:

a plurality of channels, each including:

a plurality of banks sequentially activated at intervals of a predetermined time in response to a refresh command;

a pulse generator configured to generate a pulse signal having a predetermined pulse width in response to the refresh command;

a comparator, when the refresh command is input to a first channel, configured to compare the refresh command with the pulse signal received from the pulse generator of a second channel and detect whether the refresh command is applied to the second channel;

a delay decision unit configured to output a control signal to determine a bank active delay time in response to an output signal of the comparator; and

a delay circuit configured to control an active delay time of the plurality of banks in response to an output signal of the delay decision unit.

2. The semiconductor device according to claim 1 , wherein:

if the refresh command is input to the first channel and to the second channel, the comparator outputs a high-level signal.

3. The semiconductor device according to claim 1 , wherein:

if the refresh command is applied to both the first channel and the second channel, the delay decision unit activates the plurality of banks by bypassing a delay circuit of the first channel.

4. The semiconductor device according to claim 1 , wherein the delay circuit sequentially delays the refresh command in response to a control signal of the delay decision unit, and outputs the delayed refresh command to the plurality of banks.

5. The semiconductor device according to claim 1 , wherein the delay circuit includes a plurality of delay units configured to sequentially delay the refresh command.

6. The semiconductor device according to claim 5 , wherein the plurality of delay units have the same delay time.

7. A semiconductor device comprising:

a first channel including a plurality of banks configured to be sequentially activated at intervals of a predetermined time according to a refresh command; and

a second channel configured to delay an initial active section of the plurality of banks by an other predetermined time upon receiving the refresh command within a predetermined pulse section,

wherein the first channel includes:

a first pulse generator configured to generate a first pulse signal having a predetermined pulse width in response to the refresh command;

a first comparator configured to determine whether the refresh command is applied to the second channel upon receiving the refresh command;

a first delay decision unit configured to output a control signal to determine a bank active delay time in response to an output signal of the first comparator; and

a first delay circuit configured to control an active delay time of the plurality of banks in response to an output signal of the first delay decision unit.

8. The semiconductor device according to claim 7 , wherein the second channel allows the plurality of banks to be sequentially activated at intervals of a predetermined time after lapse of a delay time of the initial active section.

9. The semiconductor device according to claim 7 , wherein:

if the first comparator receives the refresh command and the refresh command is applied to the first channel, the first comparator outputs a high-level signal.

10. The semiconductor device according to claim 7 , wherein:

if the refresh command is applied to both the first channel and the second channel, the first delay decision unit activates the plurality of banks by bypassing a delay circuit of the first channel.

11. The semiconductor device according to claim 7 , wherein the first delay circuit sequentially delays the refresh command in response to a control signal of the first delay decision unit, and outputs the delayed refresh command to the plurality of banks.

12. The semiconductor device according to claim 7 , wherein the first delay circuit includes a plurality of delay units configured to sequentially delay the refresh command.

13. The semiconductor device according to claim 12 , wherein the plurality of delay units have the same delay time.

14. The semiconductor device according to claim 7 , wherein the second channel includes:

a second pulse generator configured to generate a second pulse signal having a predetermined pulse width in response to the refresh command;

a second comparator configured to detect whether the refresh command is applied to the first channel upon receiving the refresh command;

a second delay decision unit configured to output a control signal to determine a bank active delay time in response to an output signal of the second comparator; and

a second delay circuit configured to control an active delay time of the plurality of banks in response to an output signal of the second delay decision unit.

15. The semiconductor device according to claim 14 , wherein:

if the second comparator receives the refresh command and the refresh command is applied to the first channel, the second comparator outputs a high-level signal.

16. The semiconductor device according to claim 14 , wherein:

if the refresh command is applied to both the first channel and the second channel, the second delay decision unit activates the plurality of banks by bypassing a delay circuit of the second channel.

17. The semiconductor device according to claim 14 , wherein the second delay circuit sequentially delays the refresh command in response to a control signal of the second delay decision unit, and outputs the delayed refresh command to the plurality of banks.

18. The semiconductor device according to claim 14 , wherein the second delay circuit includes a plurality of delay units configured to sequentially delay the refresh command.

19. The semiconductor device according to claim 18 , wherein the plurality of delay units have the same delay time.