IP Library Granted Patent US 10,176,002
Granted Patent B2
US 10,176,002 · App. 14/573,025 · Granted Jan 8, 2019

Quiesce handling in multithreaded environments

Inventors: Michael Fee (Cold Spring, NY); Ute Gaertner (Schoenaich, DE); Lisa C. Heller (Rhinebeck, NY); Thomas Koehler (Holzgerlingen, DE); Frank Lehnert (Schoenbuch, DE); Jennifer A. Navarro (Poughkeepsie, NY)
Assignee: International Business Machines Corporation
G06F9/45554G06F9/4812G06F9/5016G06F9/5088G06F9/45533G06F2209/5018G06F2209/5021
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,176,002
App. No.
14/573,025
Granted
Jan 8, 2019
Kind
B2
Abstract

Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Claims (9)

1. A method for performing a quiesce operation in a multithread environment, the method comprising:

receiving, by a system controller, a quiesce request from a thread executing on an initiating processor of a plurality of processors in a computing system, wherein the quiesce request comprises a zone quiesce request;

sending, by the system controller, a quiesce interrupt operation to one or more processors of a zone associated with the zone quiesce request;

identifying, by the system controller, that the one or more processors of the zone have reached respective interruptible points of execution for the one or more processors, wherein the one or more processors indicate the respective interruptible points of execution by setting a respective one or more bits corresponding with one or more threads executing on the one or more processors of the zone;

in response to a determination that the one or more processors of the zone have reached respective interruptible points of execution, program instructions to determine, by the system controller, a respective priority for the one or more processors of the zone with pending quiesce requests; and

program instructions to send, by the system controller, one or more commands to a quiesced processor of the one or more processors with pending quiesce requests based on the respective priority for the one or more processors of the zone with pending quiesce requests, wherein the one or more commands instruct the quiesced processor to perform one or more instructions requiring a quiesced state of the zone.

2. The method of claim 1 , wherein the zone quiesce request is for all processors connected to the system controller.

3. The method of claim 1 , wherein the zone quiesce request is for a subset of all processors connected to the system controller.

4. The method of claim 1 , wherein the one or more processors of the zone are quiesced until the quiesced processor performs the one or more instructions requiring a quiesced state of the zone.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2014
From: FEE, MICHAEL; GAERTNER, UTE; HELLER, LISA C.; KOEHLER, THOMAS; LEHNERT, FRANK; NAVARRO, JENNIFER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 034660/0700 →
Continuity (2)
Continuation 14542746 · Nov 17, 2014
Related Publication 20160139955A1 · May 19, 2016