IP Library Granted Patent US 9,866,476
Granted Patent B2
US 9,866,476 · App. 14/574,106 · Granted Jan 9, 2018

Parallel direction decode circuits for network-on-chip

Inventors: Mark A. Anders (Hillsboro, OR); Gregory K. Chen (Portland, OR); Himanshu Kaul (Portland, OR)
Assignee: Intel Corporation
H04L45/72H04L45/60H04L49/25H04L47/33H04L49/109
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Quick Facts
Patent No.
US 9,866,476
App. No.
14/574,106
Granted
Jan 9, 2018
Kind
B2
Abstract

A first packet and a first direction associated with the first packet are received. The first packet is forwarded to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet. A second direction associated with the first packet is determined. The second direction is based at least on an address of the first packet. The first packet and the second direction are forwarded through the output port of the first router to a second router.

Claims (42)

1. A processor comprising:

a first router comprising:

a plurality of input ports to receive packets;

a plurality of output ports to forward packets, an output port of the plurality of output ports comprising:

priority logic to select a packet from multiple packets to forward; and

direction logic to determine, for a packet of the multiple packets, a direction associated with the packet, wherein the direction logic is to perform the direction determination, at least in part, in parallel with the selection of the packet by the priority logic.

2. The processor of claim 1 , wherein a direction determined by the direction logic of the output port is the direction a packet should be forwarded by a router that receives the packet from the first router via the output port.

3. The processor of claim 1 , wherein an output port of the plurality of output ports is to forward the direction associated with a packet along with the packet to another router of the processor.

4. The processor of claim 1 , wherein an input port of the plurality of input ports is to receive a packet and an indication of a direction associated with the packet and forward the packet to an output port of the plurality of output ports based on the received indication.

5. The processor of claim 1 , wherein the processor comprises a plurality of routers and wherein a first input port of the plurality of input ports of the first router is to receive packets from a core of the first router and the remainder of the plurality of input ports are to receive packets from a respective router of the processor.

6. The processor of claim 1 , wherein the processor comprises a plurality of routers and wherein the output port of the plurality of output ports of the first router is to forward packets to a core of the first router and the remainder of the plurality of output ports are to forward packets to a respective router of the processor.

7. An apparatus comprising:

a first router operable to:

receive a first packet and a first direction associated with the first packet;

forward the first packet to an output port of a plurality of output ports of the first router based on the first direction associated with the first packet;

determine a second direction associated with the first packet, the second direction based at least on an address of the first packet; and

forward the first packet and the second direction through the output port of the first router to a second router.

8. The apparatus of claim 7 , wherein the second direction is further based on an address associated with the second router.

9. The apparatus of claim 7 , wherein the first router is further to select the first packet from a plurality of packets received at the output port and to forward the first packet based on the selection.

10. The apparatus of claim 9 , wherein at least a part of the selection is to occur simultaneously with at least a part of the determination of the second direction associated with the first packet.

11. The apparatus of claim 9 , wherein the first router is further to determine a direction for a second packet of the plurality of packets received at the output port.

12. The apparatus of claim 11 , wherein the first router is further to select the first packet simultaneously, at least in part, with the determination of the direction of the second packet of the plurality of packets received at the output port.

13. The apparatus of claim 7 , wherein the first packet is a reservation packet used to establish a circuit switched channel to pass through the first router.

14. A method comprising:

receiving a first packet and a first direction associated with the first packet;

forwarding the first packet to an output port of a plurality of output ports of a first router based on the first direction associated with the first packet;

determining a second direction associated with the first packet, the second direction based at least on an address of the first packet; and

forwarding the first packet and the second direction through the output port of the first router to a second router.

15. The method of claim 14 , wherein the second direction is further based on an address associated with the second router.

16. The method of claim 14 , further comprising selecting the first packet from a plurality of packets received at the output port and forwarding the first packet based on the selection.

17. The method of claim 16 , wherein at least a part of the selection is to occur simultaneously with at least a part of the determination of the second direction associated with the first packet.

18. The method of claim 14 , further comprising determining a direction for a second packet of the plurality of packets received at the output port.

19. The method of claim 14 , wherein the first packet is a reservation packet used to establish a circuit switched channel to pass through the first router.

20. A system comprising:

a plurality of cores;

a plurality of routers implementing a network on a chip, a router of the plurality of routers comprising:

a core input port to receive packets from a core of the plurality of cores;

a plurality of input ports, an input port of the plurality of input ports to receive packets from a router of the plurality of routers;

a core output port to forward packets to the core of the plurality of cores;

a plurality of output ports, an output port of the plurality of output ports to forward packets to a router of the plurality of routers, the output port to comprise:

priority logic to select a packet from multiple packets to forward; and

direction logic to determine, for a packet of the multiple packets, a direction associated with the packet, wherein the direction logic is to perform the direction determination, at least in part, in parallel with the selection of the packet by the priority logic.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2015
From: ANDERS, MARK A.; CHEN, GREGORY K.; KAUL, HIMANSHU
To: INTEL CORPORATION
Reel/Frame 034716/0831 →
Continuity (1)
Related Publication 20160182367A1 · Jun 23, 2016