LDMOS with adaptively biased gate-shield
View Patent ↗An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.
1. A lateral diffusion field effect transistor and an associated control circuit comprising:
a source region of doped semiconductor material that is electrically coupled to a metallic source contact;
a first doped drain region of doped semiconductor material that has a lower dopant concentration than the source region;
a second doped drain region of doped semiconductor material that: (1) forms an electrically conductive path between the metallic drain contact and the first doped drain region; and (2) has a higher dopant concentration than the first doped drain region;
a channel that separates the source region and the first doped drain region;
a gate electrode located above the channel and separated from the channel by a gate dielectric; and
a shield plate located above the gate electrode and the first doped drain region, and separated from the first doped drain region, the gate electrode, and the source contact by an interlayer dielectric;
wherein the control circuit includes a delay circuit, is integrated on a monolithic substrate with the lateral diffusion field effect transistor, and:
applies a variable voltage to the shield plate that: (1) pulls majority carriers in the first doped drain region towards the shield plate before the transistor is switched on; and (2) pushes majority carriers in the first doped drain region away from the shield plate before the transistor is switched off;
ramps the variable voltage in a first direction from a first voltage to a second voltage;
ramps the variable voltage in a second direction from the second voltage to the first voltage;
begins ramping the voltage before the transistor is switched on and completes ramping the voltage after the transistor is switched on; and
begins ramping the voltage before the transistor is switched off and completes ramping the voltage after the transistor is switched off.
2. The lateral diffusion field effect transistor and the associated control circuit of claim 1 , wherein the associated control circuit:
sets the variable voltage to a negative voltage that is below ground at a time when the transistor is switched off.
3. The lateral diffusion field effect transistor and the associated control circuit of claim 1 , wherein the gate shield further comprises:
a first tapered extension located on one side of the first doped drain region, wherein a thickest portion of the first tapered extension is located on a gate side end of the first doped drain region; and
a second tapered extension located on an opposite side of the first doped drain region, wherein a thickest portion of the second tapered extension is located on the gate side end of the first doped drain region.
4. The lateral diffusion field effect transistor and the associated control circuit of claim 3 , wherein the first and second tapered extensions:
are located above the gate electrode;
are biased by the variable voltage at the same level as the shield plate; and
shield the lateral diffusion field effect transistor from an adjacent lateral diffusion field effect transistor.
5. The lateral diffusion field effect transistor and the associated control circuit of claim 3 , wherein the first and second tapered extensions:
are formed in the same substrate as the lateral diffusion field effect transistor; and
comprise heavily doped semiconductor material.
6. The lateral diffusion field effect transistor and an associated control circuit of claim 1 , wherein the delay circuit introduces hysteresis to ramping in the first direction as compared to the second direction.
7. A lateral diffusion field effect transistor and an associated control circuit comprising:
a source region of doped semiconductor material that is ohmically coupled to a metallic source contact;
a first doped drain region of doped semiconductor material that has a lower dopant concentration than the source region, wherein the source region and the first doped drain region have a matching conductivity type;
a second doped drain region of doped semiconductor material that: (1) forms an electrically conductive path between the metallic drain contact and the first doped drain region; (2) has the matching conductivity type; and (3) has a higher dopant concentration than the first doped drain region;
a channel that separates the source region and the first doped drain region, wherein the channel has an opposite conductivity type to the matching conductivity type, and wherein the first doped drain region extends at least twice as far from the channel as the source region extends from the channel;
a gate electrode located above the channel and separated from the channel by a gate dielectric, wherein a control voltage applied to the gate electrode controls a flow of current in the channel; and
a shield plate located above the gate electrode and the first doped drain region, and insulated from the first doped drain region, the gate electrode, and the source contact by an interlayer dielectric;
wherein the shield plate is electrically insulated from the gate electrode; and
wherein the control circuit includes a delay circuit, is integrated on a monolithic substrate with the lateral diffusion field effect transistor, and:
applies a variable voltage to the shield plate that: (1) pulls majority carriers in the first doped drain region towards the shield plate before the transistor is switched on; and (2) pushes majority carriers in the first doped drain region away from the shield plate before the transistor is switched off;
ramps the variable voltage in a first direction from a first voltage to a second voltage;
ramps the variable voltage in a second direction from the second voltage to the first voltage;
begins ramping the voltage before the transistor is switched on and completes ramping the voltage after the transistor is switched on; and
begins ramping the voltage before the transistor is switched off and completes ramping the voltage after the transistor is switched off.
8. The lateral diffusion field effect transistor and the associated control circuit of claim 7 , wherein the associated control circuit:
sets the variable voltage to a negative voltage that is below ground at a time when the transistor is switched off.
9. The lateral diffusion field effect transistor and the associated control circuit of claim 7 , the gate shield further comprising:
a first tapered extension located on one side of the first doped drain region, wherein a thickest portion of the first tapered extension is located on a gate side end of the first doped drain region; and
a second tapered extension located on an opposite side of the first doped drain region, wherein a thickest portion of the second tapered extension is located on the gate side end of the first doped drain region.
10. The lateral diffusion field effect transistor and the associated control circuit of claim 9 , wherein the first and second tapered extensions:
are located above the gate electrode;
are biased by the variable voltage at the same level as the shield plate; and
shield the lateral diffusion field effect transistor from an adjacent lateral diffusion field effect transistor.
11. The lateral diffusion field effect transistor and the associated control circuit of claim 9 , wherein the first and second tapered extensions:
are formed in the same substrate as the lateral diffusion field effect transistor; and
comprise heavily doped semiconductor material.
12. The lateral diffusion field effect transistor and an associated control circuit of claim 7 , wherein the delay circuit introduces hysteresis to ramping in the first direction as compared to the second direction.
13. A lateral diffusion field effect transistor comprising:
a source region electrically coupled to a metallic source contact;
a lightly doped drain region of doped semiconductor material that has a lower dopant concentration than the source region, and that is separated from the source region by a channel;
a highly doped drain region that forms an electrically conductive path between a metallic drain contact and the lightly doped drain region;
a gate electrode located above the channel and separated from the channel by a gate dielectric; and
a gate shield located above the gate electrode and the lightly doped drain region, and separated from the lightly doped drain region, the gate electrode, and the source contact by a dielectric layer;
wherein a control circuit, is integrated on a monolithic substrate with the lateral diffusion field effect transistor and:
applies a variable voltage to the gate shield that: (1) accumulates a top layer of the lightly doped drain region before the transistor is switched on; and (2) depletes the top layer of the lightly doped drain region before the transistor is switched off;
ramps the variable voltage in a first direction from a first voltage to a second voltage;
ramps the variable voltage in a second direction from the second voltage to the first voltage;
begins ramping the voltage before the transistor is switched on and completes ramping the voltage after the transistor is switched on; and
begins ramping the voltage before the transistor is switched off and completes ramping the voltage after the transistor is switched off.
14. The lateral diffusion field effect transistor of claim 13 , wherein the control circuit:
sets the variable voltage to a negative voltage that is below ground at a time when the transistor is switched off.
15. The lateral diffusion field effect transistor of claim 13 , the gate shield further comprising:
a first tapered extension located on one side of the lightly doped drain region, wherein a thickest portion of the first tapered extension is located on a gate side end of the lightly doped drain region; and
a second tapered extension located on an opposite side of the lightly doped drain region, wherein a thickest portion of the second tapered extension is located on the gate side end of the lightly doped drain region.
16. The lateral diffusion field effect transistor of claim 15 , wherein the first and second tapered extensions:
are located above the gate electrode;
are biased by the variable voltage at the same level as the gate shield; and
shield the lateral diffusion field effect transistor from an adjacent lateral diffusion field effect transistor.
17. The lateral diffusion field effect transistor of claim 15 , wherein the first and second tapered extensions:
are formed in the same substrate as the lateral diffusion field effect transistor; and
comprise heavily doped semiconductor material.
18. The lateral diffusion field effect transistor of claim 13 , wherein the delay circuit introduces hysteresis to ramping in the first direction as compared to the second direction.