IP Library Granted Patent US 9,281,009
Granted Patent B1
US 9,281,009 · App. 14/575,634 · Granted Mar 8, 2016

Data storage device employing variable size interleave written track segments

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Quick Facts
Patent No.
US 9,281,009
App. No.
14/575,634
Granted
Mar 8, 2016
Kind
B1
Abstract

A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. Data is encoded into a first number of codewords, and the first number of codewords are interleave written to a first segment of a first data track. Data is encoded into a second number of codewords, and the second number of codewords are interleave written to a second segment of the first data track. The first number of codewords is different than the second number of codewords, and a size of the first segment is different than a size of the second segment.

Claims (223)

1. A data storage device comprising:

a disk comprising a plurality of data tracks;

a head; and

control circuitry configured to:

encode data into a first number of codewords;

interleave write the first number of codewords to a first segment of a first data track;

encode data into a second number of codewords; and

interleave write the second number of codewords to a second segment of the first data track;

wherein the first number is different than the second number and a size of the first segment is different than a size of the second segment.

2. The data storage device as recited in claim 1 , wherein:

the first data track comprises an integer number N sect of data sectors;

the first segment comprises a first integer L 0 of the data sectors; and

the second segment comprises a second integer L 1 of the data sectors.

3. The data storage device as recited in claim 2 , wherein the second segment comprises one less data sector than the first segment.

4. The data storage device as recited in claim 3 , wherein the control circuitry is further configured to compute L 0 according to:

L

0

=

L

targ

-

(

L

targ

-

(

N

sect

mod

L

targ

)

)

mod

L

targ

N

sect

L

targ

where L targ represents a target number of data sectors for the first segment.

5. The data storage device as recited in claim 4 , wherein the first data track comprises an integer N L0 of the first segments and an integer N L1 of the second where:

N

L

1

=

(

(

L

targ

-

(

N

sect

mod

L

targ

)

)

mod

L

targ

)

mod

N

sect

L

targ

N

L

0

=

N

sect

L

targ

-

N

L

1

.

6. The data storage device as recited in claim 5 , wherein the control circuitry is further configured to compute L 0 , N L0 and N L1 on the fly when executing a write command.

7. The data storage device as recited in claim 5 , wherein the control circuitry is further configured to compute L 0 , N L0 and N L1 on the fly when executing a read command.

8. A method of operating a data storage device, the method comprising:

encoding data into a first number of codewords;

interleave writing the first number of codewords to a first segment of a first data track on a disk;

encoding data into a second number of codewords; and

interleave writing the second number of codewords to a second segment of the first data track on the disk;

wherein the first number is different than the second number and a size of the first segment is different than a size of the second segment.

9. The method as recited in claim 8 , wherein:

the first data track comprises an integer number N sect of data sectors;

the first segment comprises a first integer L 0 of the data sectors; and

the second segment comprises a second integer L 1 of the data sectors.

10. The method as recited in claim 9 , wherein the second segment comprises one less data sector than the first segment.

11. The method as recited in claim 10 , further comprising computing L 0 according to:

L

0

=

L

targ

-

(

L

targ

-

(

N

sect

mod

L

targ

)

)

mod

L

targ

N

sect

L

targ

where L targ represents a target number of data sectors for the first segment.

12. The method as recited in claim 11 , wherein the first data track comprises an integer N L0 of the first segments and an integer N L1 of the second segments where:

N

L

1

=

(

(

L

targ

-

(

N

sect

mod

L

targ

)

)

mod

L

targ

)

mod

N

sect

L

targ

N

L

0

=

N

sect

L

targ

-

N

L

1

.

13. The method as recited in claim 12 , further comprising computing L 0 , N L0 and N L1 on the fly when executing a write command.

14. The method as recited in claim 12 , further comprising computing L 0 , N L0 and N L1 on the fly when executing a read command.

Assignments (8)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 6, 2015
From: BURTON, DERRICK E.; THERRIEN, MICHAEL J.; BANH, THAO HIEU; CHAN, TOM S.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 036735/0923 →