SEMICONDUCTOR PHOTOMULTIPLIER
The present disclosure relates to a semiconductor photomultiplier comprising a a substrate; an array of photosensitive elements formed on a first major surface of the substrate; a plurality of primary bus lines interconnecting the photosensitive elements; at least one segmented secondary bus line provided on a second major surface of the substrate which is operably coupled to one or more terminals; and multiple vertical interconnect access (via) extending through the substrate operably coulping the primary bus lines to the at least one segmented secondary bus line.
1 . A semiconductor photomultiplier comprising:
a substrate;
an array of photosensitive elements formed on a first major surface of the substrate;
a plurality of primary bus lines interconnecting the photosensitive elements;
at least one segmented secondary bus line provided on a second major surface of the substrate which is operably coupled to one or more terminals; and
multiple vertical interconnect access (vias) extending through the substrate operably coulping the primary bus lines to the at least one segmented secondary bus line.
2 . A semiconductor photomultiplier as claimed in claim 1 , wherein the photosensitive element comprises a single photon avalanche diode (SPAD).
3 . A semiconductor photomultiplier as claimed in claim 2 , wherein a quench element is associated with each SPAD.
4 . A semiconductor photomultiplier as claimed in claim 3 , wherein the quench element is a passive component resistor.
5 . A semiconductor photomultiplier as claimed in claim 3 , wherein the quench element is an active component transistor.
6 . A semiconductor photomultiplier as claimed in claim 1 , wherein each segment of the segmented secondary bus line has an associated via coupled to a corresponding primary bus line.
7 . A semiconductor photomultiplier as claimed in claim 1 , wherein each photosensitive element is part of a microcell.
8 . A semiconductor photomultiplier as claimed in claim 7 , wherein at least some of the segments of the segmented secondary bus line are of equal length in order to equalise the signal delays from the microcells to the one or more terminals.
9 . A semiconductor photomultiplier as claimed in claim 7 , wherein the length of at least some of the primary bus lines are of equal length in order to equalise the signal delays from the microcells to the one or more terminals.
10 . A semiconductor photomultiplier as claimed in claim 7 , wherein each microcell comprises a photodiode.
11 . A semiconductor photomultiplier as claimed in claim 10 , wherein each microcell comprises a resistor coupled in series to the photodiode.
12 . A semiconductor photomultiplier as claimed in claim 11 , further comprising a capacitive element.
13 . A semiconductor photomultiplier as claimed in claim 1 , wherein the interconnected photosensitive elements are arranged in a grid configuration.
14 . A semiconductor photomultiplier as claimed in claim 13 , wherein the primary buses lines are parallel to columns in the grid configuration.
15 . A semiconductor photomultiplier as claimed in claim 14 , wherein at least some of the primary bus lines extend between the columns.
16 . A semiconductor photomultiplier as claimed claim 1 , wherein the primary and secondary bus lines are perpendicular to each other.
17 . A semiconductor photomultiplier as claimed in claim 1 , wherein each photosensitive element comprises an avalanche photodiode or a single photon avalanche diode.
18 . A semiconductor photomultiplier as claimed in claim 13 , wherein each interconnected photosensitive element comprises a quench resistor coupled in series to the avalanche photodiode or a single photon avalanche diode.
19 . A substrate comprising:
an array of photosensitive elements formed on a first major surface of the substrate;
a plurality of primary bus lines interconnecting the photosensitive elements;
at least one segmented secondary bus line provided on a second major surface of the substrate which is operably coupled to one or more terminals; and
multiple vertical interconnect access (vias) extending through the substrate operably coulping the primary bus lines to the at least one segmented secondary bus line.
20 . A method of fabricating a semiconductor photomultiplier; the method comprising:
forming an array of photosensitive elements on a first major surface of a substrate;
providing a plurality of primary bus lines interconnecting the photosensitive elements;
providing at least one segmented secondary bus line on a second major surface of the substrate which is operably coupled to one or more terminals; and
providing multiple vertical interconnect access (vias) extending through the substrate operably coulping the primary bus lines to the at least one segmented secondary bus line.