IP Library Granted Patent US 9,910,088
Granted Patent B2
US 9,910,088 · App. 14/578,813 · Granted Mar 6, 2018

Methods and apparatus for sensor diagnostics including programmable self-test signals

Inventors: Shaun D. Milano (Dunbarton, NH); Georges El Bacha (Manchester, NH); Michael C. Doogue (Bedford, NH); William P. Taylor (Amherst, NH)
Assignee: ALLEGRO MICROSYSTEMS, LLC
G01R31/2884G01R31/2829G01R31/3187G01R33/00G01R33/0023G01R33/02G01R33/07G01R33/09G01R33/091G01R35/00H01L2224/48091H01L2224/48247H01L2224/48257H01L2924/181
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Quick Facts
Patent No.
US 9,910,088
App. No.
14/578,813
Granted
Mar 6, 2018
Kind
B2
Abstract

Methods and apparatus to provide an integrated circuit having a magnetic sensing element and fault detection module coupled to the sensing element, the fault detection module including circuitry to detect a fault condition and to self-test operation of the circuitry for detecting the fault condition. In illustrative embodiments, a fault pin indicates the fault condition.

Claims (42)

1. An integrated circuit, comprising:

a magnetic sensing element;

fault detection module coupled to the sensing element, the fault detection module including circuitry to detect a fault condition and to self-test operation of the circuitry for detecting the fault condition; and

a fault pin to indicate the fault condition, wherein the fault pin comprises an input/output pin such that pulling the fault pin to a given voltage level for a given time provides a self-test request to initiate the self-test operation, and

wherein the fault detection module includes at least one switch to cycle through connections to known voltage and ground signals and verify expected fault and no fault signals on the fault pin for the self-test operation of the circuitry for detecting the fault condition.

2. The integrated circuit according to claim 1 , wherein the fault detection module includes a window comparator having at least one threshold associated with the fault condition.

3. The integrated circuit according to claim 2 , wherein the at least one threshold corresponds to a short circuit.

4. The integrated circuit according to claim 3 , wherein the short circuit is located in a signal path extending from the window comparator to the magnetic sensing element.

5. The integrated circuit according to claim 2 , wherein the fault pin is activated to a given state upon fault detection by the at least one threshold.

6. The integrated circuit according to claim 1 , wherein self-test signals of the self-test operation are programmable in duration.

7. A method, comprising:

coupling a magnetic sensing element to fault detection module in an integrated circuit;

providing the fault detection module to include circuitry to detect a fault condition and to self-test operation of the circuitry for detecting the fault condition;

providing self-test signals; and

providing a fault pin to indicate the fault condition,

wherein the fault pin comprises an input/output pin such that pulling the fault pin to a given voltage level for a given time provides a self-test request to initiate the self-test operation, and

wherein the fault detection module includes at least one switch to cycle through connections to known voltage and ground signals and verify expected fault and no fault signals on the fault pin for the self-test operation of the circuitry for detecting the fault condition.

8. The method according to claim 7 , wherein the fault detection module includes a window comparator having at least one threshold associated with the fault condition.

9. The method according to claim 8 , wherein the at least one threshold corresponds to a short circuit condition.

10. The method according to claim 9 , wherein the short circuit condition is located in a signal path extending from the window comparator to the magnetic sensing element.

11. The method according to claim 8 , wherein the fault pin is activated to a given state upon fault detection by the at least one threshold.

12. The method according to claim 8 , wherein the fault condition includes a current level above a threshold.

13. The method according to claim 8 , wherein the given time of the self-test request is programmable.

14. The method according to claim 8 , wherein the given time of the self-test request corresponds to power up initiation of self-test request.

15. The method according to claim 8 , wherein the self-test operation is entered only when an applied magnetic field is below a magnetic field threshold.

16. The method according to claim 8 , further including controlling a voltage on the fault pin to provide an acknowledge signal indicating entrance into the self-test operation.

17. The method according to claim 16 , wherein an amount of time the acknowledge signal is active is programmable.

18. The method according to claim 16 , further including controlling the voltage level on the fault pin to provide results from the self-test operation.

19. The method according to claim 18 , further including timing the voltage level on the fault pin to indicate a pass or a fail of the self-test operation.

20. The method according to claim 19 , wherein a transition of the voltage level at a first time indicates pass, a transition of the voltage level at a second indicates a sensor test fail, and a transition of the voltage level at a third time indicates a fault failure.

21. The method according to claim 20 , wherein the first, second, and third times are programmable.

22. The method according to claim 7 , further including initiating the self-test operation after a temperature change of greater than a temperature threshold.

23. The method according to claim 7 , wherein the integrated circuit comprises a package having exactly four pins.

24. The method according to claim 7 , further including employing a die supported by a leadframe having a region cutout from the leadframe, wherein the location of the magnetic sensing element is aligned with the region to reduce Eddy currents.

25. The method according to claim 7 , wherein the self-test is terminated when a magnetic field above a flux threshold is detected.

26. The method according to claim 7 , wherein the integrated circuit comprises a linear current sensor.

27. The method according to claim 7 , wherein self-test signals of the self-test operation are programmable in duration.

28. An integrated circuit, comprising:

a magnetic sensing element;

fault detection module coupled to the sensing element, the fault detection module including circuitry to detect a fault condition and to self-test operation of the circuitry for detecting the fault condition, wherein the fault detection module includes a window comparator having at least one threshold associated with the fault condition; and

a fault pin to indicate the fault condition,

wherein the fault pin comprises an input/output pin such that pulling the fault pin to a given voltage level for a given time provides a self-test request to initiate the self-test operation, and wherein the fault detection module includes at least one switch to cycle through connections to known voltage and ground signals and verify expected fault and no fault signals on the fault pin for the self-test operation of the circuitry for detecting the fault condition.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2015
From: MILANO, SHAUN D.; EL BACHA, GEORGES; DOOGUE, MICHAEL C.; TAYLOR, WILLIAM P.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 034697/0014 →
Continuity (2)
Provisional Application 61920827 · Dec 26, 2013
Related Publication 20150185279A1 · Jul 2, 2015