Thyristor based optical and gate and thyristor-based electrical and gate
View Patent ↗An optical AND gate is provided that includes an optical thyristor configured to receive first and second digital optical signal inputs. The optical AND gate further includes control circuitry operably coupled to terminals of said optical thyristor. The control circuitry is configured to control switching operation of said optical thyristor in response to the ON/OFF states of the first and second digital optical signal inputs such that the optical thyristor produces a digital output signal that represents the AND function of the first and second digital optical signal inputs. In another aspect, an AND gate is provided that includes a thyristor and control circuitry operably coupled to terminals of the thyristor. The control circuitry is configured to receive first and second digital electrical signal inputs and control switching operation of the thyristor in response to the levels of the first and second digital electrical signal inputs such that the thyristor produces a digital output signal that represents the AND function of the first and second digital electrical signal inputs.
1. An optical AND gate comprising:
an optical thyristor defined by an epitaxial layer structure that includes a bottom n-type cathode region, an intermediate p-type region formed above the bottom n-type cathode region, an intermediate n-type region formed above the intermediate p-type region, and a top p-type anode region formed above the intermediate n-type region, wherein the optical thyristor includes an anode terminal electrically coupled to the top p-type anode region, an n-type injector terminal electrically coupled to the intermediate n-type region, a p-type injector terminal electrically coupled to the intermediate p-type region, and a cathode terminal electrically coupled to the bottom n-type cathode region, wherein the optical thyristor is configured to receive first and second digital optical signal inputs; and
a control circuitry operably coupled to the optical thyristor, the control circuitry comprising:
a p-channel HFET transistor having gate and source terminals connected to a positive voltage supply and a drain terminal connected to the n-type injector terminal; and
an n-channel HFET transistor having gate and source terminals connected to ground, and a drain terminal connected to the p-type injector terminal, wherein the control circuitry is configured to control switching operation of the optical thyristor in response to ON/OFF states of the first and second digital optical signal inputs such that the optical thyristor produces a digital output signal that represents an AND function of the first and second digital optical signal inputs.
2. The optical AND gate of claim 1 , wherein the optical thyristor produces a digital electrical signal that represents the AND function of the first and second digital optical signal inputs.
3. The optical AND gate of claim 1 , wherein the optical thyristor produces a digital optical signal that represents the AND function of the first and second digital optical signal inputs.
4. The optical AND gate of claim 3 , wherein the intermediate n-type and intermediate p-type regions include an n-type modulation doped quantum well (QW) structure and a p-type modulation doped QW structure, respectively.
5. The optical AND gate of claim 4 , wherein the n-channel HFET transistor includes an n-type QW channel formed by the n-type modulation doped QW structure.
6. The optical AND gate of claim 3 , wherein the epitaxial layer structure comprises group III-V materials.
7. An AND gate comprising:
a thyristor defined by an epitaxial layer structure that includes a bottom n-type cathode region, an intermediate p-type region formed above the bottom n-type cathode region, an intermediate n-type region formed above the intermediate p-type region, and a top p-type anode region formed above the intermediate n-type region, wherein the thyristor includes an anode terminal electrically coupled to the top p-type anode region, an n-type injector terminal electrically coupled to the intermediate n-type region, a p-type injector terminal electrically coupled to the intermediate p-type region, and a cathode terminal electrically coupled to the bottom n-type cathode region; and
a control circuitry operably coupled to the thyristor, that receives first and second digital electrical signal inputs, the control circuitry comprising:
a first p-channel HFET transistor having a source terminal connected to a positive voltage supply, a gate terminal that receives the first digital electrical signal input, and a drain terminal connected to the n-type injector terminal;
a first n-channel HFET transistor having a source terminal connected to ground, a gate terminal that receives the first digital electrical signal input, and a drain terminal connected to the n-type injector terminal;
a second n-channel HFET transistor having a drain terminal connected to the positive voltage supply, a gate terminal that receives the second digital electrical signal input, and a source terminal connected to the p-type injector terminal; and
a second p-channel HFET transistor having a drain terminal connected to ground, a gate terminal that receives the second digital electrical signal input, and a source terminal connected to the p-type injector terminal, wherein the control circuitry is configured to control switching operation of the thyristor in response to levels of the first and second digital electrical signal inputs such that the thyristor produces a digital output signal that represents an AND function of the first and second digital electrical signal inputs.
8. The AND gate of claim 7 , wherein the thyristor produces a digital electrical signal that represents the AND function of the first and second digital electrical signal inputs.
9. The AND gate of claim 7 , wherein the thyristor produces a digital optical signal that represents the AND function of the first and second digital electrical signal inputs.
10. The AND gate of claim 7 , wherein the intermediate n-type and intermediate p-type regions include an n-type modulation doped quantum well (QW) structure and a p-type modulation doped QW structure, respectively.
11. The AND gate of claim 10 , wherein at least one of the first and second n-channel HFET transistors includes an n-type QW channel formed by the n-type modulation doped QW structure.
12. The AND gate of claim 7 , wherein the epitaxial layer structure comprises group III-V materials.