IP Library Granted Patent US 9,195,260
Granted Patent B2
US 9,195,260 · App. 14/579,068 · Granted Nov 24, 2015

Semiconductor device, radio communication terminal using same, and clock frequency control method

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Quick Facts
Patent No.
US 9,195,260
App. No.
14/579,068
Granted
Nov 24, 2015
Kind
B2
Abstract

A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU 0 ) that operates according to the clock signal, a storage circuit (e.g., IC 0 ) that is activated according to access from the arithmetic circuit CPU 0 , a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU 0 to the storage circuit IC 0 , and when the number of accesses increases, outputs a request signal (e.g., psreq 1 ), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq 1.

Claims (12)

1. A semiconductor device comprising:

a clock generation circuit that generates a clock signal;

an arithmetic circuit that operates according to the clock signal;

a storage circuit that is activated according to access from the arithmetic circuit;

a memory access detection unit that detects a number of accesses from the arithmetic circuit to the storage circuit and applies a weight to the number of accesses; and

a clock control circuit that lowers the frequency of the clock signal when a variation of the weighted number of accesses exceeds a variation threshold.

2. The semiconductor device according to claim 1 , wherein the weight is a value for one access.

3. A clock frequency control method for a clock signal supplied to a semiconductor device with an arithmetic circuit that operates according to the clock signal and a storage circuit that is activated according to access from the arithmetic circuit, the clock frequency control method comprising:

detecting a number of accesses from the arithmetic circuit to the storage circuit;

applying a weight to the number of accesses; and

lowering a frequency of the clock signal when a variation of the weighted number of accesses exceeds a variation threshold.

4. The method according to claim 3 , wherein the weight is a value for one access.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Mar 17, 2015
From: RENESAS MOBILE CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 035186/0340 →