METHOD AND SYSTEM FOR OPERATING GALLIUM NITRIDE ELECTRONICS
An electronic circuit comprising a driver and a main transistor are provided. The driver may include a bias voltage generator, a supplementary transistor, and an output driver. The bias voltage generator may be configured to receive a voltage input and generate a biased voltage output based on the voltage input. The supplementary transistor may have a gate coupled to the biased voltage output of the bias voltage generator, and a source of the supplementary transistor providing a current to the bias voltage generator. The output driver may be configured to receive the biased voltage output from the bias voltage generator and the voltage input, receive the voltage input, and output a drive voltage. The main transistor of the electronic circuit may have a gate, a coupled to the drive voltage, and a drain coupled to a drain of the supplementary transistor.
1 - 19 . (canceled)
20 . An electronic circuit comprising:
a first driver configured to generate an input voltage;
a second driver coupled to the first driver, the second driver configured to receive the input voltage and generate a drive voltage based on the input voltage; and
a gallium nitride (GaN) transistor having a gate, a drain, and a source, wherein the gate is coupled to the second driver, and configured to receive the drive voltage.
21 . The electronic circuit of claim 20 , wherein the second driver comprises:
a bias voltage generator configured to receive the input voltage and generate a biased voltage output based on the input voltage;
a supplementary transistor coupled to the bias voltage generator; and
an output driver configured to:
receive the biased voltage output from the bias voltage generator;
receive the voltage input from the first driver; and
output the drive voltage.
22 . The electronic circuit of claim 21 , wherein the supplementary transistor comprises a gate, a drain, and a source, wherein:
the gate of the supplementary transistor is coupled to the biased voltage output of the bias voltage generator; and
the source of the supplementary transistor provides a current to the bias voltage generator.
23 . The electronic circuit of claim 22 , wherein the drain of the GaN transistor is coupled to the drain of the supplementary transistor.
24 . The electronic circuit of claim 22 , wherein the supplementary transistor is a transistor formed of GaN, such that:
the drain of the supplementary transistor comprises a GaN substrate and a drain contact;
the source of the supplementary transistor is separated from the GaN substrate by a drift region and comprises a source contact;
the drift region of the supplementary transistor comprises a first GaN epitaxial layer coupled to the GaN substrate; and
the gate of the supplementary transistor comprises a second GaN epitaxial layer coupled to the first GaN epitaxial layer and a gate contact coupled to the biased voltage output of the bias voltage generator.
25 . The electronic circuit of claim 22 , the second driver further comprising a current monitor configured to detect a current from the drain to the source of the supplementary transistor and output a regulated current, wherein the output driver further is configured to receive the regulated current from the current monitor.
26 . The electronic circuit of claim 21 , wherein the supplementary transistor and the gallium nitride transistor are junction gate field-effect transistors.
27 . The electronic circuit of claim 21 , wherein the output driver is a voltage converter.
28 . The electronic circuit of claim 20 , wherein the second driver is driven by a voltage at the drain of the gallium nitride transistor.
29 . The electronic circuit of claim 20 , wherein the second driver and the gallium nitride transistor are co-packaged in a same package.
30 . The electronic circuit of claim 29 wherein the second driver and the gallium nitride transistor are on different dies.
31 . The electronic circuit of claim 20 , wherein the first driver is an insulated-gate bipolar transistor (IGBT) driver and the second driver is a gallium nitride (GaN) junction gate field-effect transistor (JFET) driver.
32 . The electronic circuit of claim 20 , wherein the input voltage is greater than the drive voltage.
33 . A method of operating a gallium nitride (GaN) junction gate field-effect transistor (JFET), the method comprising:
receiving, at a GaN JFET driver, an input voltage;
generating, by the GaN JFET driver, a biased voltage output based on the input voltage; and
providing, by the GaN JFET driver, an output drive voltage to the GaN JFET, wherein the output drive voltage is based on the biased voltage output.
34 . The method of claim 33 , further comprising:
monitoring a current of a supplementary transistor to provide a current value;
receiving, at an output driver, the biased voltage output, the current value, and the input voltage; and
generating the output drive voltage based on the biased voltage output, the current value, and the input voltage.
35 . The method of claim 34 wherein the current value is based on the current from the drain to the source of the supplementary transistor.
36 . The method of claim 33 wherein the input voltage comprises a pulsed input voltage.
37 . The method of claim 33 wherein the output drive voltage is characterized by a lower amplitude than the input voltage.
38 . The method of claim 33 wherein the output drive voltage is generated by a voltage converter.
39 . The method of claim 38 wherein the voltage converter is driven by a voltage at a drain of the GaN JFET.