Method of manufacturing a misfet on an SOI substrate
View Patent ↗Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
1. A method of manufacturing a semiconductor device including a semiconductor substrate, a first insulating film formed over the semiconductor substrate and a first semiconductor layer formed over the first insulating film, the method comprising:
(a) forming a gate insulating film of a MISFET over the first semiconductor layer;
(b) forming a gate electrode of the MISFET over the gate insulating film;
(c) forming first side walls over the first semiconductor layer and side surfaces of the gate electrode;
(d) after the step (c), forming epitaxial layers over the first semiconductor layer and each side surface of the first side walls;
(e) after the step (d), removing the side walls;
(f) after the step (e), forming first impurity regions of a first conductive type in the first semiconductor layer by ion implantation;
(g) after the step (f), forming second side walls over the first impurity regions and the side surfaces of the gate electrode; and
(h) after the step (g), forming second impurity regions of the first conductive type in the epitaxial layers and the first semiconductor layer by an ion implantation method,
wherein the first impurity regions are used for a part of source and drain region of the MISFET, and
wherein the second impurity regions are used for a part of the source and drain region of the MISFET and have larger impurity concentration than the first impurity regions.
2. The method of manufacturing a semiconductor device according to the claim 1 , further comprising:
(i) after the step (h), forming silicide layers over the gate electrode and the epitaxial layers.
3. The method of manufacturing a semiconductor device according to the claim 1 , further comprising:
(j) between the steps (e) and (g), forming third impurity regions of a second conductive type being opposite to the first conductive type in the semiconductor substrate by ion implantation.
4. The method of manufacturing a semiconductor device according to the claim 1 , wherein the first side walls are formed of silicon nitride film, respectively.
5. The method of manufacturing a semiconductor device according to the claim 1 , wherein the second side walls are formed of silicon nitride film, respectively.
6. The method of manufacturing a semiconductor device according to the claim 1 , wherein the first conductive type is an n-type.
7. The method of manufacturing a semiconductor device according to the claim 3 , wherein the first conductive type is an n-type, and the second conductive type is a p-type.