IP Library Granted Patent US 9,577,426
Granted Patent B2
US 9,577,426 · App. 14/580,932 · Granted Feb 21, 2017

Switching circuits for extracting power from an electric power source and associated methods

Inventors: Anthony J. Stratakos (Kentfield, CA); Michael D. McJimsey (Danville, CA); Ilija Jergovic (Palo Alto, CA); Alexandr Ikriannikov (Castro Valley, CA); Artin Der Minassians (Oakland, CA); Kaiwei Yao (San Jose, CA); David B. Lidsky (Oakland, CA); Marco A. Zuniga (Berkeley, CA); Ana Borisavljevic (Pleasanton, CA)
Assignee: Volterra Semiconductor LLC
H02J1/102H02J3/383H02M3/158H03K17/102H03K17/122H03K17/145H03K17/693H01L2224/16225H01L2224/48091H02J2001/106H03K2217/0036H03K2217/0054Y02E10/563Y10T307/685Y10T307/696Y10T307/707
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Quick Facts
Patent No.
US 9,577,426
App. No.
14/580,932
Granted
Feb 21, 2017
Kind
B2
Abstract

An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.

Claims (46)

1. An integrated circuit chip, comprising:

a first input port and a first output port;

first and second transistors electrically coupled in series across the first input port, the second transistor also electrically coupled across the first output port and adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state;

first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states; and

first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port;

wherein the first controller circuitry is adapted to:

control the first driver circuitry such that the first and second transistors cooperate to transfer power from the first input port to the first output port during a first operating mode of the first controller circuitry,

control the first driver circuitry such that the second transistor shunts the first output port during a second operating mode of the first controller circuitry, and

operate the first controller circuitry in its second operating mode upon occurrence of an event selected from the group consisting of (1) voltage across the first input port being below a threshold value, (2) voltage across the first input port being above a threshold value, (3) power transferred from the first input port to the first output port being below a threshold value, (4) a magnitude of current flowing through the first input port being below a threshold value, (5) a magnitude of current flowing through the first output port exceeding a threshold value, and (6) a temperature of one or more components of the integrated circuit chip exceeding a threshold value.

2. The integrated circuit chip of claim 1 , the integrated circuit chip being a flip chip integrated circuit chip.

3. The integrated circuit chip of claim 1 , further comprising first, second, and third terminals, the first and second terminals providing an electrical interface to the first input port, and the second and third terminals providing an electrical interface to the first output port.

4. The integrated circuit chip of claim 1 , wherein the first controller circuitry is operable to at least substantially maximize an average value of a voltage at an intermediate switching node where the first and second transistors are electrically coupled.

5. The integrated circuit chip of claim 1 , wherein the first controller circuitry is operable to repeatedly sample an average value of a voltage at an intermediate switching node and control switching of the first transistor at least partly based on at least two successive samples of the average value of the voltage at the intermediate switching node, the intermediate switching node being a node where the first and second transistors are electrically coupled.

6. The integrated circuit chip of claim 5 , wherein a starting time of the first controller circuitry is loosely controlled.

7. The integrated circuit chip of claim 1 , wherein a frequency at which the first transistor switches between its conductive and non-conductive states is loosely controlled.

8. An integrated circuit chip, comprising:

a first input port and a first output port;

first and second transistors electrically coupled in series across the first input port, the second transistor also electrically coupled across the first output port and adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state;

first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states;

first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port;

a second input port and a second output port;

third and fourth transistors electrically coupled in series across the second input port, the fourth transistor also electrically coupled across the second output port and adapted to provide a path for current flowing through the second output port when the third transistor is in its non-conductive state;

second driver circuitry for driving gates of the third and fourth transistors to cause the transistors to switch between their conductive and non-conductive states; and

second controller circuitry for controlling the second driver circuitry such that the third and fourth transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the second input port.

9. The integrated circuit chip of claim 8 , the first and second controller circuitry being part of a common controller.

10. The integrated circuit chip of claim 8 , the first and second output ports being electrically coupled in series within the integrated circuit chip.

11. The integrated circuit chip of claim 8 , wherein:

the second controller circuitry is operable to:

control the second driver circuitry such that the third and fourth transistors cooperate to transfer power from the second input port to the second output port during a first operating mode of the second controller circuitry, and

control the second driver circuitry such that the fourth transistor shunts the second output port during a second operating mode of the second controller circuitry.

12. A photovoltaic system, comprising:

a photovoltaic cell; and

an integrated circuit chip, including:

an output port for electrically coupling to a load,

first and second transistors electrically coupled in series across the photovoltaic cell, the second transistor also electrically coupled across the output port and adapted to provide a path for current flowing through the output port when the first transistor is in its non-conductive state,

driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states, and

controller circuitry for controlling the driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from the photovoltaic cell,

wherein the controller circuitry is adapted to:

control the driver circuitry such that the first and second transistors cooperate to transfer power from the photovoltaic cell to the output port during a first operating mode of the controller circuitry,

control the driver circuitry such that the second transistor shunts the output port during a second operating mode of the controller circuitry, and

operate the controller circuitry in its second operating mode upon occurrence of an event selected from the group consisting of (1) voltage across the photovoltaic cell being below a threshold value, (2) voltage across the photovoltaic cell being above a threshold value, (3) power transferred from the photovoltaic cell to the output port being below a threshold value, (4) a magnitude of current flowing through the photovoltaic cell being below a threshold value, (5) a magnitude of current flowing through the output port exceeding a threshold value, and (6) a temperature of one or more components of the integrated circuit chip exceeding a threshold value.

13. The photovoltaic system of claim 12 , the integrated circuit chip being a flip chip integrated circuit chip.

14. The photovoltaic system of claim 12 , the controller circuitry configured to cause the first and second transistors switch between their conductive and non-conductive states at a switching frequency of at least 200 kilohertz.

15. The photovoltaic system of claim 14 , wherein:

the integrated circuit chip further includes an input port interfacing the first and second transistors with the photovoltaic cell; and

ripple current flowing through the input port is filtered primarily by one or more multi-layer ceramic capacitors.

Assignments (2)
CHANGE OF NAME Recorded Dec 18, 2015
From: VOLTERRA SEMICONDUCTOR CORPORATION
To: VOLTERRA SEMICONDUCTOR LLC
Reel/Frame 037336/0323 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 23, 2014
From: STRATAKOS, ANTHONY J.; MCJIMSEY, MICHAEL D.; JERGOVIC, ILIJA; IKRIANNIKOV, ALEXANDR; DER MINASSIANS, ARTIN; YAO, KAIWEI; LIDSKY, DAVID B.; ZUNIGA, MARCO A.; BORISAVLJEVIC, ANA
To: VOLTERRA SEMICONDUCTOR CORPORATION
Reel/Frame 034578/0709 →
Continuity (3)
Division 13211997 · Aug 17, 2011
Provisional Application 61375012 · Aug 18, 2010
Related Publication 20150108960A1 · Apr 23, 2015