Method and apparatus for improving read performance of a solid state drive

1. A method for improving performance of a solid state drive, the method comprising:

initiating, by a controller of the solid state drive, a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive; and

performing the repacking of the data stored in the non-volatile memory of the solid state drive by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.

2. The method of claim 1 , the method further comprising:

receiving a read request from a host for a plurality of logical blocks; and

in response to determining that the plurality of logical blocks are stored physically contiguously in the increasing order, dispatching a single request to one or more non-volatile memory chips of the solid state drive to fetch the plurality of logical blocks.

3. The method of claim 2 , wherein the logical blocks are represented in a smaller page size in the host than the solid state drive.

4. The method of claim 3 , wherein an indirection table in the solid state drive maintains pointers to physical memory addresses of most recent copies of valid data stored in the solid state drive, and wherein the indirection table represents the plurality of logical blocks in a same page size as the host.

5. The method of claim 1 , wherein the solid state drive is comprised of a plurality of three-dimensional NAND chips, wherein there is only one channel for each three-dimensional NAND chip of the plurality of three-dimensional NAND chips, wherein there is only one chip select for each three-dimensional NAND chip of the plurality of three-dimensional NAND chips, and wherein parallel read requests cannot be handed by the only one channel.

6. The method of claim 5 , wherein each NAND page size is 16 Kilobytes and requests from a host to the solid state drive are made in page sizes of 4 Kilobytes.

7. The method of claim 1 , wherein the repacking of data in the solid state drive is performed periodically, and wherein the placing of the logical blocks physically contiguously in the increasing order in the pre-erased locations of the non-volatile memory of the solid state drive is performed during each periodic repacking of the data in the solid state drive.

8. The method of claim 1 , wherein the placing of the logical blocks physically contiguously in the increasing order in the pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked improves read performance in comparison to the placing of the logical blocks physically contiguously in a random order in the pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.

9. An apparatus, comprising:

a plurality of non-volatile memory chips; and

a controller coupled to the plurality of non-volatile memory chips, wherein the controller is operable to:

initiate, a repacking of data stored in the plurality of non-volatile memory chips, wherein refreshing of the data stored in the plurality of non-volatile memory chips is performed during the repacking of the data stored in the plurality of non-volatile memory chips; and

perform the repacking of the data stored in the plurality of non-volatile memory chips by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the plurality of non-volatile memory chips, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.

10. The apparatus of claim 9 , wherein the controller is further operable to:

receive a read request from a host for a plurality of logical blocks; and

in response to determining that the plurality of logical blocks are stored physically contiguously in the increasing order, dispatch a single request to one or more non-volatile memory chips to fetch the plurality of logical blocks.

11. The apparatus of claim 10 , wherein the logical blocks are represented in a smaller page size in the host than the plurality of non-volatile memory chips.

12. The apparatus of claim 11 , wherein an indirection table maintains pointers to physical memory addresses of most recent copies of valid data stored in the plurality of non-volatile memory chips, and wherein the indirection table represents the plurality of logical blocks in a same page size as the host.

13. The apparatus of claim 9 , wherein the plurality of non-volatile memory chips is comprised of a plurality of three-dimensional NAND chips, and wherein there is only one channel for each three-dimensional NAND chip of the plurality of three-dimensional NAND chips, wherein there is only one chip select for each three-dimensional NAND chip of the plurality of three-dimensional NAND chips, and wherein parallel read requests cannot be handed by the only one channel.

14. The apparatus of claim 13 , wherein each NAND page size is 16 Kilobytes and requests from a host to the apparatus are made in page sizes of 4 Kilobytes.

15. The apparatus of claim 9 , wherein the repacking of data in the plurality of non-volatile memory chips is performed periodically, and wherein the placing of the logical blocks physically contiguously in the increasing order in the pre-erased locations of the plurality of non-volatile memory chips is performed during each periodic repacking of the data in the plurality of non-volatile memory chips.

16. The apparatus of claim 9 , wherein the placing of the logical blocks physically contiguously in the increasing order in the pre-erased locations while the data is being repacked improves read performance in comparison to the placing of the logical blocks physically contiguously in a random order in the pre-erased locations while the data is being repacked.

17. A system, comprising:

a solid state drive comprising a plurality of non-volatile memory chips;

a display; and

a processor coupled to the solid state drive and the display, wherein, the solid state drive is operable to:

initiate, a repacking of data stored in the plurality of non-volatile memory chips, wherein refreshing of the data stored in the plurality of non-volatile memory chips is performed during the repacking of the data stored in the plurality of non-volatile memory chips; and

perform the repacking of the data stored in the plurality of non-volatile memory chips by placing logical blocks physically contiguously in an increasing order in pre-erased locations of the plurality of non-volatile memory chips, wherein the placing of the logical blocks contiguously in the increasing order comprises placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.

18. The system of claim 17 , wherein the solid state drive is further operable to:

receive a read request from a host operating system for a plurality of logical blocks; and

in response to determining that the plurality of logical blocks are stored physically contiguously in the increasing order, dispatch a single request to one or more non-volatile memory chips to fetch the plurality of logical blocks.

19. The system of claim 18 , wherein the host operating system represents logical blocks in a smaller page size than the plurality of non-volatile memory chips.

20. The system of claim 19 , wherein an indirection table maintains pointers to physical memory addresses of most recent copies of valid data stored in the plurality of non-volatile memory chips, and wherein the indirection table represents the plurality of logical blocks in a same page size as the host operating system.

21. The system of claim 17 , wherein the plurality of non-volatile memory chips is comprised of a plurality of three-dimensional NAND chips, and wherein there is only one channel for each three-dimensional NAND chip of the plurality of three-dimensional NAND chips, wherein there is only one chip select for each three-dimensional NAND chip of the plurality of three-dimensional NAND chips, and wherein parallel read requests cannot be handed by the only one channel.

22. The system of claim 21 , wherein each NAND page size is 16 Kilobytes and requests from a host operating system to the solid state drive are made in page sizes of 4 Kilobytes.

23. The system of claim 17 , wherein the repacking of data in the plurality of non-volatile memory chips is performed periodically, and wherein the placing of the logical blocks physically contiguously in the increasing order in the pre-erased locations of the plurality of non-volatile memory chips is performed during each periodic repacking of the data in the plurality of non-volatile memory chips.

24. The system of claim 17 , wherein the placing of the logical blocks physically contiguously in the increasing order in the pre-erased locations while the data is being repacked improves read performance in comparison to the placing of the logical blocks physically contiguously in a random order in the pre-erased locations while the data is being repacked.