Timing recovery in a high speed link
View Patent ↗Systems and methods for high speed communications are described herein. In certain aspects, the systems and methods include innovative transceiver architectures and techniques for re-timing, multiplexing, de-multiplexing and transmitting data. The systems and methods can be used to achieve reliable high-speed point-to-point communication between different electronic devices, computing devices, storage devices and peripheral devices.
1. A clock and data recovery circuit comprising:
a data recovery analog-to-digital converter (ADC) configured to receive an input signal and to generate a first digital output signal;
a clock recovery ADC configured to receive the input signal and to generate a second digital output signal, wherein the data recovery ADC has a higher resolution than the clock recovery ADC;
a timing control circuit configured to receive the second digital output signal and to generate a clock control signal based on the second digital output signal; and
a clock generation unit configured to control a timing of the data recovery ADC and a timing of the clock recovery ADC based on the clock control signal.
2. The clock and data recovery circuit of claim 1 , wherein the first digital output signal comprises at least 3 bits, and wherein the second digital output signal comprises at least 2 bits.
3. The clock and data recovery circuit of claim 1 , wherein a latency of the data recovery ADC is greater than a latency of the clock recovery ADC.
4. The clock and data recovery circuit of claim 1 , wherein the clock generation unit is configured to generate a sampling clock signal and to control a timing of analog-to-digital conversion operations of the clock recovery ADC based on the sampling clock signal, wherein the clock control signal is configured to control at least one of a frequency or a phase of the sampling clock signal.
5. The clock and data recovery circuit of claim 4 , wherein both the clock recovery ADC and the data recovery ADC receive the sampling clock signal.
6. The clock and data recovery circuit of claim 1 , wherein the clock generation unit comprises a digitally controlled oscillator (DCO).
7. The clock and data recovery circuit of claim 1 , wherein the timing control circuit comprises digital logic circuitry.
8. The clock and data recovery circuit of claim 7 , wherein the timing control circuit generates the clock control signal based on the second digital output signal entirely in the digital domain.
9. The clock and data recovery circuit of claim 1 , wherein the input signal comprises a non-return-to-zero (NRZ) signal or a 4-level pulse amplitude modulation (PAM-4) signal.
10. A transceiver comprising:
an equalizer configured to receive a data signal and to generate a clock and data recovery (CDR) input signal based on equalizing the data signal; and
a CDR circuit comprising:
a data recovery analog-to-digital converter (ADC) configured to receive the CDR input signal and to generate a first digital output signal;
a clock recovery ADC configured to receive the CDR input signal and to generate a second digital output signal, wherein the data recovery ADC has a higher resolution than the clock recovery ADC;
a timing control circuit configured to receive the second digital output signal and to generate a clock control signal based on the second digital output signal; and
a clock generation unit configured to control a timing of the data recovery ADC and a timing of the clock recovery ADC based on the clock control signal.
11. The transceiver of claim 10 , further comprising a digital signal processor (DSP) configured to receive the first digital output signal.
12. The transceiver of claim 10 , wherein the transceiver comprises a host side and a line side, wherein the equalizer is configured to receive the data signal on the host side from an electronic device.
13. The transceiver of claim 10 , wherein the transceiver comprises a host side and a line side, wherein the equalizer is configured to receive the data signal on the line side from a cable.
14. The transceiver of claim 10 , wherein the first digital output signal comprises at least 3 bits, and wherein the second digital output signal comprises at least 2 bits.
15. The transceiver of claim 10 , wherein the timing control circuit generates the clock control signal based on the second digital output signal entirely in the digital domain.
16. The transceiver of claim 10 , wherein the CDR input signal comprises a non-return-to-zero (NRZ) signal or a 4-level pulse amplitude modulation (PAM-4) signal.
17. A method of clock and data recovery, the method comprising:
generating a first digital output signal based on an input signal using a data recovery analog-to-digital converter (ADC);
generating a second digital output signal based on the input signal using a clock recovery ADC, wherein the data recovery ADC has a higher resolution than the clock recovery ADC;
generating a clock control signal based on the second digital output signal using a timing control circuit; and
controlling a timing of the data recovery ADC and a timing of the clock recovery ADC based on the clock control signal.
18. The method of claim 17 , further comprising:
generating a sampling clock signal using a clock generation unit;
controlling at least one of a frequency or a phase of the sampling clock signal using the clock control signal; and
controlling a timing of analog-to-digital conversion operations of the clock recovery ADC based on the sampling clock signal.
19. The method of claim 17 , wherein generating the first digital output signal comprises generating at least 3 bits, and wherein generating the second digital output signal comprises generating at least 2 bits.
20. The method of claim 17 , wherein generating the clock control signal based on the second digital output signal comprises processing the second digital output signal entirely in the digital domain.