IP Library Granted Patent US 9,368,083
Granted Patent B2
US 9,368,083 · App. 14/582,048 · Granted Jun 14, 2016

Liquid crystal display device adapted to partial display

Inventors: Goro Sakamaki (Tokyo, JP); Ki-hwak Yun (Tokyo, JP)
Assignee: Synaptics Display Devices GK
G09G3/3648G09G3/3655G09G3/3688G02F2001/133391G09G2300/0408G09G2310/027G09G2310/04
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Quick Facts
Patent No.
US 9,368,083
App. No.
14/582,048
Granted
Jun 14, 2016
Kind
B2
Abstract

A liquid crystal display device includes a liquid crystal display panel; and a driver driving the liquid crystal display panel. The liquid crystal display panel includes: a first substrate on which subpixels each including a pixel electrode are integrated; and a second substrate opposed to the first substrate, a plurality of common electrodes being formed on the second substrate. The display region of the liquid crystal display panel is divided into a plurality of sections respectively corresponding to the common electrodes. When a partial display in which an image is selectively displayed in a selected section is performed, the liquid crystal driver drives the common electrode corresponding to the selected section to a predetermined common voltage level, sets the common electrodes corresponding to the non-selected sections to a predetermined reference level, and sets pixel electrodes of subpixels in the non-selected sections to the reference voltage level.

Claims (56)

1. A liquid crystal display device, comprising:

a liquid crystal display panel; and

a liquid crystal driver configured to drive said liquid crystal display panel,

wherein said liquid crystal display panel includes:

a first substrate on which a plurality of subpixels each including a pixel electrode are integrated; and

a second substrate opposed to said first substrate, a plurality of common electrodes being formed on said second substrate,

wherein a display region of said liquid crystal display panel is divided into a plurality of sections respectively corresponding to said plurality of common electrodes, and

wherein the liquid crystal driver is configured to:

when a partial display in which an image is selectively displayed in a section selected from said plurality of sections is performed, drive a common electrode corresponding to said selected section of said plurality of common electrodes to a predetermined common voltage level, set a common electrode corresponding to a non-selected section of said plurality of common electrodes to a predetermined reference level, drive pixel electrodes of subpixels in said selected section of said plurality of subpixels to pixel voltage levels corresponding to image data, and set pixel electrodes of subpixels in said non-selected section of said plurality of subpixels to said reference voltage level.

2. The liquid crystal display device according to claim 1 , wherein:

said reference voltage level is substantially equal to a circuit ground level of said liquid crystal driver.

3. The liquid crystal display device according to claim 1 , further comprising:

a gate drive circuit configured to:

drive gate lines disposed in said display region of said liquid crystal display panel.

4. The liquid crystal display device according to claim 3 , wherein:

the gate drive circuit is further configured to:

sequentially drive said gate lines in said display region when said partial display is performed and when a full-screen display in which an image is displayed in the entire display region is performed.

5. The liquid crystal display device according to claim 1 , further comprising:

a gate drive circuit configured to:

drive gate lines disposed in said display region of said liquid crystal display panel.

6. The liquid crystal display device according to claim 5 , wherein the gate driver circuit is further configured to:

sequentially drive said gate lines in said display region for a predetermined number of vertical sync periods after said partial display is started, when said partial display is performed.

7. The liquid crystal display device according to claim 6 , wherein the gate driver circuit is further configured to:

after sequentially driving said gate lines for the predetermined number of vertical sync periods, sequentially drive only gate lines which intersect said selected section in vertical sync periods following said predetermined number of vertical sync periods.

8. A liquid crystal driver for driving a liquid crystal display panel including: a first substrate on which a plurality of subpixels each including a pixel electrode and a plurality of source lines connected with said plurality of subpixels are integrated; and a second substrate opposed to said first substrate, a plurality of common electrodes being formed on said second substrate, said liquid crystal driver comprising:

a common electrode drive circuit configured to drive said plurality of common electrodes; and

a source drive circuit configured to drive said plurality of source lines,

wherein said common electrode drive circuit is configured to:

when a partial display in which an image is selectively displayed in a section selected from a plurality of sections is performed, said plurality of sections being defined in a display region of said liquid crystal display panel so as to respectively correspond to said plurality of common electrodes, drive a common electrode corresponding to said selected section of said plurality of common electrodes to a predetermined common voltage level and set a common electrode corresponding to non-selected section of said plurality of common electrodes to a predetermined reference level, and

wherein said source drive circuit is configured to:

when a partial display in which an image is selectively displayed in a section selected from a plurality of sections is performed, drive pixel electrodes of subpixels in said selected section to pixel voltage levels corresponding to image data via said source lines and set pixel electrodes of subpixels in said non-selected section to said reference voltage level.

9. The liquid crystal driver according to claim 8 , wherein:

said reference voltage level is substantially equal to a circuit ground level of said liquid crystal driver.

10. The liquid crystal driver according to claim 8 , further comprising:

a control circuit configured to control a gate drive circuit driving gate lines disposed in said display region of said liquid crystal display panel.

11. The liquid crystal driver according to claim 10 , wherein:

said control circuit is configured to control said gate drive circuit to sequentially drive substantially all of said gate lines in said display region either when said partial display is performed and when a full-screen display in which an image is displayed in the entire display region is performed.

12. The liquid crystal driver according to claim 8 , further comprising:

a control circuit configured to control a gate drive circuit that is configured to drive gate lines disposed in said display region of said liquid crystal display panel.

13. The liquid crystal driver according to claim 12 , wherein:

the control circuit is further configured to control said gate drive circuit to sequentially drive substantially all of said gate lines in said display region for a predetermined number of vertical sync periods after said partial display is started.

14. The liquid crystal driver according to claim 13 , wherein:

the control circuit is further configured to control said gate drive circuit to sequentially drive only gate lines which intersect said selected section in vertical sync periods following said predetermined number of vertical sync periods, after driving substantially all of said gate lines in said display region.

15. A driving method for driving a liquid crystal display panel including: a first substrate on which a plurality of subpixels each including a pixel electrode are integrated; and a second substrate opposed to said first substrate, a plurality of common electrodes being formed on said second substrate, and said method comprising:

performing a partial display in which an image is selectively displayed in a section selected from a plurality of sections defined in a display region of aid liquid crystal display panel to respectively correspond to said plurality of common electrodes,

wherein in said performing said partial display, a common electrode corresponding to said selected section of said plurality of common electrodes is driven to a predetermined common voltage level, a common electrode corresponding to non-selected section of said plurality of common electrodes is set to a predetermined reference level, pixel electrodes of subpixels in said selected section of said plurality of subpixels are driven to pixel voltage levels corresponding to image data and pixel electrodes of subpixels in said non-selected section of said plurality of subpixels are set to said reference voltage level.

16. The driving method according to claim 15 , wherein:

said reference voltage level is substantially equal to a circuit ground level of a liquid crystal driver driving said liquid crystal display panel.

17. The driving method according to claim 15 , wherein:

performing said partial display comprises sequentially driving substantially all gate lines disposed in said display region for a predetermined number of vertical sync periods after said partial display is started.

18. The driving method according to claim 17 , wherein:

performing said partial display further comprises sequentially driving only gate lines which intersect said selected section in vertical sync periods following said predetermined number of vertical sync periods, after sequentially driving substantially all of said gate lines.

19. The driving method according to claim 15 , further comprising:

sequentially driving substantially all gate lines disposed in said display region when said partial display is performed.

20. The driving method according to claim 15 , further comprising:

sequentially driving substantially all gate lines disposed in said display region when a full-screen display in which an image is displayed in the entire display region is performed.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2024
From: SYNAPTICS JAPAN GK
To: SYNAPTICS INCORPORATED
Reel/Frame 067793/0211 →
SECURITY INTEREST Recorded Sep 27, 2017
From: SYNAPTICS INCORPORATED
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 044037/0896 →
CHANGE OF NAME Recorded Aug 8, 2016
From: SYNAPTICS DISPLAY DEVICES GK
To: SYNAPTICS JAPAN GK
Reel/Frame 039711/0862 →
CHANGE OF NAME Recorded May 29, 2015
From: SYNAPTICS DISPLAY DEVICES KK
To: SYNAPTICS DISPLAY DEVICES GK
Reel/Frame 035797/0036 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2014
From: SAKAMAKI, GORO; YUN, KI-HWAK
To: SYNAPTICS DISPLAY DEVICES KK
Reel/Frame 034590/0915 →
Priority Claims (1)
JP 2013-269054 · Dec 26, 2013 · national
Continuity (1)
Related Publication 20150187295A1 · Jul 2, 2015