Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)
View Patent ↗An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.
1. A system comprising:
a digital-to-analog converter (DAC) operable to generate a reference value according to a previous codeword, the previous codeword having been generated according to an asynchronous successive approximation step;
a comparator operable to generate an indication signal according to a comparison between an analog signal level and the reference value;
a timer operable to generate a timeout signal that preempts the indication signal; and
a logic unit operable to generate a preemptive decision according to the timeout signal, the preemptive decision being a current codeword.
2. The system of claim 1 , wherein the generation of the preemptive decision comprises a setting of one or more bits of the current codeword without performance of additional comparisons to determine the one or more bits.
3. The system of claim 2 , wherein the one or more bits of the current codeword are set based on the sign of the difference between an input analog voltage and the reference value.
4. The system of claim 2 , wherein:
if a most-recently decided bit of the previous codeword is 0, then the one or more bits of the current codeword are set to 1; and
if a most-recently decided bit of the previous codeword is 1, then the one or more bits of the current codeword are set to 0.
5. The system of claim 2 , wherein how many bits are in the one or more bits is determined based on a range of overlapping codes of the DAC.
6. The system of claim 1 , wherein the timer is operable to generate the timeout signal based on a threshold that is determined one or both of adaptively and dynamically.
7. The system of claim 6 , wherein the timer is operable to determine the threshold so as to guarantee that a magnitude of a difference between the analog signal level and an analog signal level corresponding to the current codeword is within a determined range.
8. The system of claim 1 , wherein an input-voltage-to-output-code characteristic of the DAC comprises overlapping codes.
9. The system of claim 1 , wherein the timer is operable to adjust timing of the timeout signal based on temperature.
10. The system of claim 1 , wherein the timer is operable to adjust timing of the timeout signal based on power supply voltage.
11. A method comprising:
generating, by a digital-to-analog converter (DAC), a reference value according to a previous codeword, the previous codeword having been generated according to an asynchronous successive approximation step;
generating, by a comparator, an indication signal according to a comparison between an analog signal level and the reference value;
generating, by a timer, a timeout signal that preempts the indication signal; and
generating, by a logic unit, a preemptive decision according to the timeout signal, the preemptive decision being a current codeword.
12. The method of claim 11 , wherein the generating the preemptive decision comprises setting one or more bits of the current codeword without performing additional comparisons to determine the one or more bits.
13. The method of claim 12 , comprising setting the one or more bits of the current codeword based on the sign of the difference between an input analog voltage and the reference value.
14. The method of claim 12 , wherein:
if a most-recently decided bit of the previous codeword is 0, setting the one or more bits of the current codeword to 1; and
if a most-recently decided bit of the previous codeword is 1, setting the one or more bits of the current codeword to 0.
15. The method of claim 12 , wherein how many bits are in the one or more bits is determined based on a range of overlapping codes of the DAC.
16. The method of claim 11 , comprising generating, by the timer, the timeout signal based on a threshold that is determined one or both of adaptively and dynamically.
17. The method of claim 16 , comprising determining, by the timer, the threshold so as to guarantee that a magnitude of a difference between the analog signal level and an analog signal level corresponding to the current codeword is within a determined range.
18. The method of claim 11 , wherein an input-voltage-to-output-code characteristic of the DAC comprises overlapping codes.
19. The method of claim 11 , adjusting, by the timer, timing of the timeout signal based on temperature.
20. The method of claim 11 , adjusting, by the timer, timing of the timeout signal based on power supply voltage.