IP Library › Granted Patent US 9,584,127
Granted Patent B2
US 9,584,127 · App. 14/586,810 · Granted Feb 28, 2017

Inverter, driving circuit and display panel

Inventors: Dong Qian (Shanghai, CN); Yue Li (Shanghai, CN); Tong Zhang (Shanghai, CN); Zhiliang Wang (Shanghai, CN); Liyuan Luo (Shanghai, CN)
Assignees: SHANGHAI TIANMA AM-OLED CO., LTD.; 03;TIANMA MICRO-ELECTRONICS CO., LTD.
H03K19/0944H03K19/00315G09G3/3266G09G2310/0291H02M2001/0054
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Quick Facts
Patent No.
US 9,584,127
App. No.
14/586,810
Granted
Feb 28, 2017
Kind
B2
Abstract

An inverter includes first, second, third, fourth, and fifth transistors, and first and second capacitors. The transistors and capacitors are connected in such way that the reverse conduction of the second transistor is prevented through controlling the gate electrode of the second transistor and maintaining the electrical potential at the gate electrode of the fifth transistor by the second capacitor. The electrical potential at the gate electrode of the fifth transistor is maintained stable when a first clock signal changes from high to low (when the first to fifth transistors are NMOS transistors) or from low to high (when the first to fifth transistors are PMOS transistors), so that the output signal of the inverter may not be affected by a change of the first clock signal, thus enabling the inverter to generate a stable output signal and a display panel comprising the inverter to obtain a better display effect.

Claims (47)

1. An inverter, comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor; wherein:

a gate electrode of the first transistor is electrically connected with an initial signal input terminal for receiving an initial signal, a source electrode of the first transistor is electrically connected with a first electrical level signal input terminal for receiving a first electrical level signal, and a drain electrode of the first transistor is electrically connected with a source electrode of the second transistor and a gate electrode of the fifth transistor;

a drain electrode of the second transistor is electrically connected, via the first capacitor, with a first clock signal input terminal for receiving a first clock signal;

a gate electrode of the third transistor is electrically connected with a second clock signal input terminal for receiving a second clock signal, a source electrode of the third transistor is electrically connected with the drain electrode of the second transistor, and a drain electrode of the third transistor is electrically connected with a second electrical level signal input terminal for receiving a second electrical level signal;

a gate electrode of the fourth transistor is electrically connected with the initial signal input terminal, a source electrode of the fourth transistor is electrically connected with the first electrical level signal input terminal, and a drain electrode of the fourth transistor is electrically connected with an output terminal for outputting an output signal; and

a source electrode of the fifth transistor is electrically connected with the output terminal, and a drain electrode of the fifth transistor is electrically connected with the second electrical level signal input terminal;

wherein reverse conduction of the second transistor is prevented through control over the gate electrode of the second transistor, the second capacitor is configured to maintain an electrical potential at the gate electrode of the fifth transistor, and the initial signal and the output signal are inverse to each other.

2. The inverter according to claim 1 , wherein, the gate electrode of the fifth transistor is electrically connected with the output terminal via the second capacitor; or the gate electrode of the fifth transistor is electrically connected with the first electrical level signal input terminal via the second capacitor.

3. The inverter according to claim 2 , wherein, the gate electrode of the second transistor is electrically connected with the drain electrode of the second transistor.

4. The inverter according to claim 3 , wherein, working status of the inverter comprises:

a first stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal is transmitted to the gate electrode of the second transistor via the third transistor and controls the gate electrode of the second transistor to turn on, and then transmitted to the gate electrode of the fifth transistor via the second transistor and controls the fifth transistor to turn on, and then the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the first stage;

a second stage, in which the initial signal controls the first transistor and the fourth transistor to turn on, the first electrical level signal is transmitted to the gate electrode of the fifth transistor via the first transistor and controls the fifth transistor to turn off, the second clock signal controls the third transistor to turn off, and the first electrical level signal is transmitted to the output terminal via the fourth transistor as an output signal of the second stage;

a third stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal is transmitted to the gate electrode of the second transistor via the third transistor and controls the second transistor to turn on, and then transmitted to the gate electrode of the fifth transistor via the second transistor and controls the fifth transistor to turn on, then the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the third stage; and

a fourth stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn off, the first clock signal controls the electrical potential at the gate electrode of the second transistor via the first capacitor to turn on the second transistor, the electrical potential at the gate electrode of the second transistor controls the electrical potential at the gate electrode of the fifth transistor via the second transistor to turn on the fifth transistor, and the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the fourth stage.

5. The inverter according to claim 2 , wherein, the gate electrode of the second transistor is electrically connected with the second electrical level signal input terminal.

6. The inverter according to claim 5 , wherein, working status of the inverter comprises:

a first stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal controls the second transistor to turn on and is transmitted to the gate electrode of the fifth transistor sequentially via the third transistor and the second transistor to control the fifth transistor to turn on, and then second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the first stage;

a second stage, in which the initial signal controls the first transistor and the fourth transistor to turn on, the first electrical level signal is transmitted to the gate electrode of the fifth transistor via the first transistor and controls the fifth transistor to turn off, the second electrical level signal continues controlling to turn on the second transistor to turn on, the second clock signal controls the third transistor to turn off, and the first electrical level signal is transmitted to the output terminal via the fourth transistor as an output signal of the second stage;

a third stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal continues controlling the second transistor to turn on, the second electrical level signal is transmitted to the gate electrode of the fifth transistor sequentially via the third transistor and the second transistor to control the fifth transistor to turn on, and the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the third stage; and

a fourth stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn off, the second electrical level signal continues controlling the second transistor to turn on, the first clock signal controls the electrical potential at the drain electrode of the second transistor via the first capacitor, the electrical potential at the drain electrode of the second transistor controls the electrical potential at the gate electrode of the fifth transistor via the second transistor to turn on the fifth transistor, and the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the fourth stage.

7. The inverter according to claim 1 , wherein, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all NMOS transistors or PMOS transistors.

8. The inverter according to claim 1 , wherein, the initial signal, the output signal, the first clock signal and the second clock signal are all pulse signals, wherein the first clock signal and the second clock signal are inverse to each other.

9. The inverter according to claim 1 , wherein, the first electrical level signal and the second electrical level signal are both constant signals.

10. A driving circuit, comprising an inverter, wherein the inverter comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first capacitor and a second capacitor; wherein:

a gate electrode of the first transistor is electrically connected with an initial signal input terminal for receiving an initial signal, a source electrode of the first transistor is electrically connected with a first electrical level signal input terminal for receiving a first electrical level signal, and a drain electrode of the first transistor is electrically connected with a source electrode of the second transistor and a gate electrode of the fifth transistor;

a drain electrode of the second transistor is electrically connected, via the first capacitor, with a first clock signal input terminal for receiving a first clock signal;

a gate electrode of the third transistor is electrically connected with a second clock signal input terminal for receiving a second clock signal, a source electrode of the third transistor is electrically connected with the drain electrode of the second transistor, and a drain electrode of the third transistor is electrically connected with a second electrical level signal input terminal for receiving a second electrical level signal;

a gate electrode of the fourth transistor is electrically connected with the initial signal input terminal, a source electrode of the fourth transistor is electrically connected with the first electrical level signal input terminal, and a drain electrode of the fourth transistor is electrically connected with an output terminal for outputting an output signal; and

a source electrode of the fifth transistor is electrically connected with the output terminal, and a drain electrode of the fifth transistor is electrically connected with the second electrical level signal input terminal;

wherein reverse conduction of the second transistor is prevented through control over the gate electrode of the second transistor, the second capacitor is configured to maintain an electrical potential at the gate electrode of the fifth transistor, and the initial signal and the output signal are inverse to each other.

11. A display panel, comprising the driving circuit in claim 10 .

12. The driving circuit according to claim 10 , wherein, the gate electrode of the fifth transistor is electrically connected with the output terminal via the second capacitor; or the gate electrode of the fifth transistor is electrically connected with the first electrical level signal input terminal via the second capacitor.

13. The driving circuit according to claim 12 , wherein, the gate electrode of the second transistor is electrically connected with the drain electrode of the second transistor.

14. The driving circuit according to claim 13 , wherein, working status of the inverter comprises:

a first stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal is transmitted to the gate electrode of the second transistor via the third transistor and controls the gate electrode of the second transistor to turn on, and then transmitted to the gate electrode of the fifth transistor via the second transistor and controls the fifth transistor to turn on, and then the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the first stage;

a second stage, in which the initial signal controls the first transistor and the fourth transistor to turn on, the first electrical level signal is transmitted to the gate electrode of the fifth transistor via the first transistor and controls the fifth transistor to turn off, the second clock signal controls the third transistor to turn off, and the first electrical level signal is transmitted to the output terminal via the fourth transistor as an output signal of the second stage;

a third stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal is transmitted to the gate electrode of the second transistor via the third transistor and controls the second transistor to turn on, and then transmitted to the gate electrode of the fifth transistor via the second transistor and controls the fifth transistor to turn on, then the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the third stage; and

a fourth stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn off, the first clock signal controls the electrical potential at the gate electrode of the second transistor via the first capacitor to turn on the second transistor, the electrical potential at the gate electrode of the second transistor controls the electrical potential at the gate electrode of the fifth transistor via the second transistor to turn on the fifth transistor, and the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the fourth stage.

15. The driving circuit according to claim 12 , wherein, the gate electrode of the second transistor is electrically connected with the second electrical level signal input terminal.

16. The driving circuit according to claim 15 , wherein, working status of the inverter comprises:

a first stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal controls the second transistor to turn on and is transmitted to the gate electrode of the fifth transistor sequentially via the third transistor and the second transistor to control the fifth transistor to turn on, and then second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the first stage;

a second stage, in which the initial signal controls the first transistor and the fourth transistor to turn on, the first electrical level signal is transmitted to the gate electrode of the fifth transistor via the first transistor and controls the fifth transistor to turn off, the second electrical level signal continues controlling to turn on the second transistor to turn on, the second clock signal controls the third transistor to turn off, and the first electrical level signal is transmitted to the output terminal via the fourth transistor as an output signal of the second stage;

a third stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn on, the second electrical level signal continues controlling the second transistor to turn on, the second electrical level signal is transmitted to the gate electrode of the fifth transistor sequentially via the third transistor and the second transistor to control the fifth transistor to turn on, and the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the third stage; and

a fourth stage, in which the initial signal controls the first transistor and the fourth transistor to turn off, the second clock signal controls the third transistor to turn off, the second electrical level signal continues controlling the second transistor to turn on, the first clock signal controls the electrical potential at the drain electrode of the second transistor via the first capacitor, the electrical potential at the drain electrode of the second transistor controls the electrical potential at the gate electrode of the fifth transistor via the second transistor to turn on the fifth transistor, and the second electrical level signal is transmitted to the output terminal via the fifth transistor as an output signal of the fourth stage.

17. The driving circuit according to claim 10 , wherein, the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are all NMOS transistors or PMOS transistors.

18. The driving circuit according to claim 10 , wherein, the initial signal, the output signal, the first clock signal and the second clock signal are all pulse signals, wherein the first clock signal and the second clock signal are inverse to each other.

19. The driving circuit according to claim 10 , wherein, the first electrical level signal and the second electrical level signal are both constant signals.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2022
From: SHANGHAI TIANMA AM-OLED CO.,LTD.; TIANMA MICRO-ELECTRONICS CO., LTD.
To: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.; WUHAN TIANMA MICROELECTRONICS CO., LTD.SHANGHAI BRANCH; TIANMA MICRO-ELECTRONICS CO., LTD.
Reel/Frame 059619/0730 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2014
From: QIAN, DONG; LI, YUE; ZHANG, TONG; WANG, ZHILIANG; LUO, LIYUAN
To: SHANGHAI TIANMA AM-OLED CO., LTD.; TIANMA MICRO-ELECTRONICS CO., LTD.
Reel/Frame 034604/0406 →
Priority Claims (1)
CN 2014 1 0538426 · Oct 13, 2014 · national
Continuity (1)
Related Publication 20160105184A1 · Apr 14, 2016