Systems and methods for increasing the transmission speed of a satellite VSAT
View Patent ↗Systems and methods are provided for increasing or decreasing the transmission speed of a VSAT used in a satellite network. A VSAT may include an ASIC and an FPGA in a transmission block of the VSAT. The ASIC includes an ASIC transmit modulator configured to modulate an input information signal, and circuitry for bypassing at least a portion of the ASIC transmit modulator. The FPGA includes circuitry for receiving a signal bypassing at least a portion of the ASIC transmit modulator, and an FPGA transmit modulator configured to modulate the bypassed signal. In implementations, the system uses the ASIC to burst format an input information signal with a payload burst segment; bypasses a transmit modulator of the ASIC after burst formatting the input information signal with the ASIC; and uses an FPGA to insert additional burst segments into the ASIC burst-formatted signal.
1. A satellite terminal, comprising:
first circuitry comprising:
a burst formatter configured to burst format an input information signal;
a first transmit modulator configured to modulate an input information signal; and
an output that bypasses at least a portion of the first transmit modulator;
second circuitry comprising:
an input coupled to the output and configured to receive a signal bypassing at a least a portion of the first transmit modulator; and
a second transmit modulator configured to modulate the bypassed signal, wherein the bypassed signal is the burst-formatted input information signal.
2. The satellite terminal of claim 1 , wherein the satellite terminal is a very-small-aperture terminal (VSAT).
3. The satellite terminal of claim 2 , wherein the VSAT comprises an indoor unit and an outdoor unit, and wherein the first circuitry is in the indoor unit.
4. The satellite terminal of claim 1 , wherein the first circuitry is an application-specific integrated circuit (ASIC) and where the second circuitry is a field programmable gate array (FPGA).
5. The satellite terminal of claim 4 , wherein the first circuitry further comprises an ASIC outdoor unit control (ODUC) signal block, and wherein the second circuitry further comprises an FPGA outdoor unit control (ODUC) signal block coupled to an output of the ASIC ODUC signal block.
6. The satellite terminal of claim 1 , further comprising a digital-to-analog converter (DAC) comprising an input and output, wherein the DAC input is coupled to an output of the second circuitry, and wherein the DAC output is coupled to a block upconverter (BUC).
7. The satellite terminal of claim 1 , wherein the second transmit modulator comprises a mapper filter, a spreader filter, and a clock domain crossing (CDC) first-in first-out (FIFO).
8. A very-small-aperture terminal (VSAT) comprising transmit circuitry for transmitting a burst modulated signal over a wireless medium, the transmit circuitry comprising:
an application-specific integrated circuit (ASIC) comprising:
an output;
an ASIC transmit modulator; and
a burst formatter configured to burst format an input information signal, wherein the burst-formatted input information signal bypasses at least a portion of the ASIC transmit modulator over the ASIC output;
a field programmable gate array (FPGA) comprising:
an input coupled to the ASIC output;
an output; and
an FPGA transmit modulator; and
a digital-to-analog converter (DAC) coupled to the FPGA output.
9. The VSAT of claim 8 , wherein the ASIC further comprises an ASIC outdoor unit control (ODUC) signal block, and wherein the FPGA further comprises an FPGA outdoor unit control (ODUC) signal block coupled to an output of the ASIC ODUC signal block.
10. The VSAT of claim 8 , wherein the DAC comprises an output coupled to a BUC.
11. The VSAT of claim 8 , wherein the transmit circuitry resides in an indoor unit of the VSAT.
12. The VSAT of claim 8 , wherein at a least a portion of the transmit circuitry resides in an outdoor unit of the VSAT.
13. A method, comprising:
using first circuitry to burst format an input information signal with a payload burst segment;
bypassing a transmit modulator of the first circuitry after burst formatting the input information signal;
using second circuitry to insert additional burst segments into the first circuitry burst-formatted signal; and
modulating the second circuitry burst-formatted signal using a transmit modulator of the second circuitry.
14. The method of claim 13 , wherein the additional burst segments comprise at least one of a unique word (UW) segment, a ramp up segment, a ramp down segment, or a pilot segment.
15. The method of claim 13 , wherein the first circuitry burst-formatted signal comprises one burst segment, wherein the one burst segment is a payload segment.
16. The method of claim 15 , wherein the first circuitry is an application-specific integrated circuit (ASIC) and the second circuitry is a field programmable gate array (FPGA).