IP Library Granted Patent US 10,474,223
Granted Patent B2
US 10,474,223 · App. 14/588,115 · Granted Nov 12, 2019

Systems, methods, and apparatuses for powerline communication

Inventors: John G. Waclawsky (Alpine, WY); Sohrab Modi (Oakland, CA)
Assignee: Echelon Corporation
G06F1/3296G06F1/266H04B3/54G06F1/3203G06F1/3209H04B2203/5425
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Quick Facts
Patent No.
US 10,474,223
App. No.
14/588,115
Granted
Nov 12, 2019
Kind
B2
Abstract

Systems, methods, and apparatuses for improved powerline communication (PLC) are described. In one embodiment, a system comprises power down hardware coupled to internal wiring of a premises to selectively power down a portion of the internal wiring on request, and at least one hardware device to transmit a request to the power down hardware to selectively power down a portion of the internal wiring on request and to transmit data using power line communication hardware of the at least one hardware device while the portion of the internal wiring is powered down.

Claims (11)

1. A system comprising:

power down hardware coupled to internal wiring of a premises to selectively power down a portion of the internal wiring on request;

wherein the power down hardware to include a sensor to sense noise on the internal wiring; and

at least one hardware device to transmit a request to the power down hardware to selectively power down a portion of the internal wiring on request in response to noise in the internal wiring and to transmit data using power line communication hardware of the at least one hardware device while the portion of the internal wiring is powered down, wherein the at least one hardware device to include a power source to power the power line communication hardware while the portion of internal wiring is powered down.

2. The system of claim 1 , wherein the at least one hardware device to include a timer to count an amount of time to accumulate data in a buffer of the at least one hardware device.

3. The system of claim 2 , wherein the at least one hardware device to include a processor and a memory to store instructions, which when executed by the processor, to cause the processor to calculate an amount of time needed to transmit data in the buffer in the at least one hardware device.

4. The system of claim 1 , wherein the at least one hardware device to include a sensor to sense noise on the internal wiring.

5. The system of claim 1 , further comprising:

a plurality of hardware devices incapable of power line communication coupled to the internal wiring.

6. The system of claim 1 , wherein the power down hardware to include a power source to power the power line communication hardware while the portion of internal wiring is powered down.

7. The system of claim 1 , wherein the power down hardware to include shutoff hardware coupled to a circuit breaker panel to selectively turn off panels.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Sep 24, 2019
From: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
To: ECHELON CORPORATION
Reel/Frame 050480/0865 →
SECURITY INTEREST Recorded Oct 8, 2018
From: ECHELON CORPORATION
To: OBSIDIAN AGENCY SERVICES, INC., AS COLLATERAL AGENT
Reel/Frame 047205/0018 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 18, 2016
From: WACLAWSKY, JOHN G.; MODI, SOHRAB
To: ECHELON CORPORATION
Reel/Frame 038310/0162 →
Continuity (1)
Related Publication 20160187962A1 · Jun 30, 2016