DOT INVERSION LAYOUT
This disclosure provides systems and apparatus for an arrangement of pixels and interconnects in a display. In one aspect, interconnect for the arrangement of pixels may be routed to reduce parasitic capacitance.
1 . A circuit including an array of display units, the circuit comprising:
a first display unit having a first electrode associated with a movable element of the first display unit and a second electrode, the first electrode coupled with a first interconnect in a first anchor region, the second electrode coupled with a second interconnect, the second interconnect routed into the first anchor region;
a second display unit having a third electrode associated with a movable element of the second display unit and a fourth electrode, third electrode coupled with a third interconnect in a second anchor region, the fourth electrode coupled with a fourth interconnect, the fourth interconnect routed into the second anchor region;
a third display unit having a fifth electrode associated with a movable element electrode of the third display unit and a sixth electrode, the fifth electrode coupled with the third interconnect in a third anchor region, the sixth electrode coupled with a fifth interconnect, the fifth interconnect routed into the third anchor region; and
a fourth display unit having a seventh electrode associated with a movable element of the fourth display unit and an eighth electrode, the seventh electrode coupled with a sixth interconnect in a fourth anchor region, the eighth electrode coupled with the second interconnect, the second interconnect routed into the fourth anchor region.
2 . The circuit of claim 1 , wherein the first, second, and sixth interconnects are capable of being at a first polarity, and the third, fourth, and fifth interconnects are capable of being at a second polarity when the first, second, and sixth interconnects are at the first polarity, the first polarity opposite to the second polarity.
3 . The circuit of claim 1 , wherein the first anchor region includes a via coupling the first interconnect with the first electrode.
4 . The circuit of claim 3 , wherein the via, the first interconnect, and the first electrode in the first anchor region are in one or more layers higher or lower than a portion of the second interconnect within the first anchor region.
5 . The circuit of claim 4 , wherein the via, the first interconnect, the first electrode, and the second interconnect are capable of being at a common polarity.
6 . The circuit of claim 1 , wherein the display units are interferometric modulators (IMODs).
7 . The circuit of claim 1 , wherein the first and the third anchor regions are at a different position relative to the first and third display units, respectively, than the second and fourth anchor regions to the second and fourth display units, respectively.
8 . The circuit of claim 7 , wherein the first and third anchor regions are closer to a first corner of the first and second display units, and the second and fourth anchor regions are closer to a second corner of the first and second display units, the first corner and the second corner being different corners of the display units.
9 . The circuit of claim 1 , further comprising:
a display including the array of display units;
a processor that is capable of communicating with the display device, the processor being configured to process image data; and
a memory device that is capable of communicating with the processor.
10 . The circuit of claim 9 , further comprising:
a driver circuit capable of sending at least one signal to the display; and
a controller capable of sending at least a portion of the image data to the driver circuit.
11 . The circuit of claim 9 , further comprising:
an image source module capable of sending the image data to the processor, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter.
12 . The circuit of claim 9 , further comprising:
an input device capable of receiving input data and to communicate the input data to the processor.
13 . A display comprising:
a first column of display units, each of the display units in the first column associated with a corresponding anchor region providing a connection to a first electrode of the associated display unit, the anchor regions of the display units in the first column being in a first arrangement relative to the associated display units in the first column; and
a second column of display units, each of the display units in the second column associated with a corresponding anchor region providing a connection to a first electrode of the associated display unit, the anchor regions of the display units in the second column being in a second arrangement relative to the associated display units in the second column, the first arrangement and the second arrangement being different.
14 . The display of claim 13 , wherein the first arrangement includes the anchor regions in a first location relative to the associated display units in the first column, the second arrangement includes the anchor regions in a second location relative to the associated display units in the second column, the first location and the second location being different.
15 . The display of claim 14 , wherein the first location relative to the associated display units is in a first corner of the display units, the second location relative to the associated display units is in a second corner of the display units, the first corner being a different corner than the second corner.
16 . The display of claim 13 , wherein the array of display units includes a first display unit in the first column and a second display unit in the second column adjacent to the first column, the anchor region of the first display unit being at a different vertical location than the anchor region of the second display unit.
17 . A display circuit including an array of display units comprising:
means for reducing parasitic capacitance between interconnects associated with electrodes of display units, the interconnects overlapping in corresponding anchor regions associated with the display units.
18 . The display circuit of claim 17 , wherein the interconnects associated with electrodes of display units include a first interconnect and a second interconnect, wherein the array of display units includes a first display unit having a movable element electrode and a second electrode, the movable element electrode coupled to the first interconnect in an anchor region, the second interconnect coupled to a second electrode of a second display unit and routed into the anchor region, and the second electrode of the first display unit is routed into the anchor region.
19 . The display circuit of claim 18 , wherein the second electrode of the first display unit is routed into the anchor region and in between the first interconnect and the second interconnect.
20 . The display circuit of claim 17 , wherein the array of display units includes:
a first display unit having a movable element electrode and a second electrode, the movable element electrode coupled with a first interconnect in a first anchor region, the second electrode coupled with a second interconnect, the second interconnect routed into the first anchor region;
a second display unit having a movable element electrode and a second electrode, the movable element electrode coupled with a third interconnect in a second anchor region, the second electrode coupled with a fourth interconnect, the fourth interconnect routed into the second anchor region;
a third display unit having a movable element electrode and a second electrode, the movable element electrode coupled with the third interconnect in a third anchor region, the second electrode coupled with a fifth interconnect, the fifth interconnect routed into the third anchor region; and
a fourth display unit having a movable element electrode and a second electrode, the movable element electrode coupled with a sixth interconnect in a fourth anchor region, the second electrode coupled with the second interconnect, the second interconnect routed into the fourth anchor region.