Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
View Patent ↗Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients.
1. A method for wireless communication, the method comprising:
receiving an analog signal on a chip;
converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC); and
reducing a blocker signal that is aliased onto a desired digital signal by a timing offset in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital signal and said blocker signal utilizing timing offset estimation and compensation circuitry.
2. The method according to claim 1 , comprising utilizing, by the timing offset estimation and compensation circuitry, a decorrelation algorithm.
3. The method according to claim 2 , comprising summing the aliased signal with an output signal from a multiplier.
4. The method according to claim 3 , comprising determining complex coupling coefficients utilizing said decorrelation algorithm on said summed signals.
5. The method according to claim 4 , comprising determining said timing offset utilizing said determined complex coupling coefficients.
6. The method according to claim 5 , comprising configuring said multiplier with a value determined from said determined timing offset.
7. The method according to claim 6 , comprising cancelling said blocker signal utilizing the configured multiplier.
8. The method according to claim 1 , comprising approximating an amplitude of said blocker signal as linear within a desired frequency bandwidth.
9. The method according to claim 1 , comprising performing a foreground estimation and timing offset compensation by generating the received analog signal utilizing a calibration tone generator on said chip.
10. The method according to claim 1 , comprising performing a background estimation and timing offset compensation utilizing an analog signal received from external to said chip.
11. The method according to claim 10 , comprising estimating a change in said timing offset utilizing the background estimation and compensation.
12. The method according to claim 1 , wherein said time interleaved ADC comprises two ADC paths with clock signals with 180 degree phase difference.
13. The method according to claim 1 , comprising estimating said timing offset based on a ratio of amplitudes of a desired analog signal associated with said desired digital signal and an analog signal associated with the blocker signal.
14. The method according to claim 1 , comprising estimating a timing mismatch for a plurality of frequency channels utilizing said timing offset estimation and compensation circuitry.
15. The method according to claim 1 , comprising reducing said blocker signal in a time domain.
16. The method according to claim 1 , comprising reducing said blocker signal in a frequency domain.
17. The method according to claim 1 , comprising reducing said blocker signal at least partially in an analog domain.
18. The method according to claim 1 , comprising reducing said blocker signal at least partially in a digital domain.
19. A system for wireless communication, the system comprising:
a chip comprising one or more circuits, said one or more circuits comprising a time interleaved analog-to-digital-converter (ADC) with two ADC paths and timing offset estimation and compensation circuitry, wherein said one or more circuits are operable to:
receive an analog signal on said chip;
convert the analog signal to a digital signal utilizing said time interleaved ADC; and
reduce a blocker signal that is generated by a timing offset between clock signals in said two ADC paths, by estimating complex coupling coefficients between a desired digital output signal and said blocker signal utilizing said timing offset estimation and compensation circuitry.
20. A system for wireless communication, the system comprising:
a chip comprising one or more circuits, said one or more circuits comprising a time interleaved analog-to-digital-converter (ADC) and timing offset estimation and compensation circuitry, wherein said one or more circuits are operable to:
receive an analog signal on said chip;
convert the analog signal to a digital signal utilizing said time interleaved ADC; and
reduce a blocker signal that is aliased onto a desired signal by timing offsets in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital output signal and said blocker signal utilizing said timing offset estimation and compensation circuitry.
21. The system according to claim 20 , wherein the timing offset estimation and compensation circuitry utilizes a decorrelation algorithm.
22. The system according to claim 21 , wherein said one or more circuits are operable to sum the aliased signal with an output signal from a multiplier.
23. The system according to claim 22 , wherein said one or more circuits are operable to determine complex coupling coefficients utilizing said decorrelation algorithm on said summed aliased and output signals.
24. The system according to claim 23 , wherein said one or more circuits are operable to determine said timing offset utilizing said determined complex coupling coefficients.
25. The system according to claim 24 , wherein said one or more circuits are operable to configure said multiplier with a value determined from said determined timing offset.
26. The system according to claim 25 , wherein said one or more circuits are operable to cancel said blocker signal utilizing the configured multiplier.
27. The system according to claim 20 , wherein said one or more circuits are operable to approximate an amplitude of said blocker signal as linear within a desired frequency bandwidth.
28. The system according to claim 20 , wherein said one or more circuits are operable to perform a foreground estimation and timing offset compensation by generating the received analog signal utilizing a calibration tone generator on said chip.
29. The system according to claim 20 , wherein said one or more circuits are operable to perform a background estimation and timing offset compensation utilizing an analog signal received from external to said chip.
30. The system according to claim 29 , wherein said one or more circuits are operable to estimate a change in said timing offset utilizing the background estimation and compensation.
31. The system according to claim 20 , wherein said one or more circuits are operable to estimate said timing offset based on a ratio of amplitudes of a desired analog signal associated with said desired digital signal and an analog signal associated with the blocker signal.
32. The system according to claim 20 , wherein said one or more circuits are operable to estimate a timing mismatch for a plurality of frequency channels utilizing said timing offset estimation and compensation circuitry.
33. The system according to claim 20 , comprising reducing said blocker signal in a time domain.
34. The system according to claim 20 , comprising reducing said blocker signal in a frequency domain.
35. The system according to claim 20 , comprising reducing said blocker signal at least partially in an analog domain.
36. The system according to claim 20 , comprising reducing said blocker signal at least partially in a digital domain.