IP Library Granted Patent US 9,191,182
Granted Patent B2
US 9,191,182 · App. 14/591,052 · Granted Nov 17, 2015

Data transmission method and associated signal transmitter

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Quick Facts
Patent No.
US 9,191,182
App. No.
14/591,052
Granted
Nov 17, 2015
Kind
B2
Abstract

A signal transmission method suitable for a signal transmitter includes: providing a plurality of clock signals with different phases, selecting some of the clock signals as a plurality of intermediate signals; transmitting the intermediate signals to a signal output circuit via a clock distribution network; selecting one of the intermediate signals as a reference clock of the signal output circuit to output data.

Claims (29)

1. A signal transmission method, suitable for a signal transmitter, comprising:

providing a plurality of clock signals with different phases;

selecting some of the clock signals as a plurality of intermediate signals;

transmitting the intermediate signals to a signal output circuit of the signal transmitter via a clock distribution network; and

selecting one of the intermediate signals as a reference clock of the signal output circuit to output a set of data.

2. The signal transmission method according to claim 1 , wherein the signal transmitter comprises eight signal output circuits that output a data byte, and the reference clock of each of the signal output circuits is selected from the intermediate signals.

3. The signal transmission method according to claim 1 , the intermediate signals being a plurality of first intermediate signals, the method further comprising:

selecting some of the clock signals as a plurality of second intermediate signals; and

selecting one of the second intermediate signals as a reference clock of another signal output circuit of the signal transmitter to output another set of data.

4. The signal transmission method according to claim 3 , wherein the signal transmitter comprises eight high-byte signal output circuits and eight low-byte signal output circuits that output a data word; the reference clock of each of the high-byte signal output circuits is selected from the first intermediate signals; the reference clock of each of the low-byte signal output circuits is selected from the second intermediate signals.

5. The signal transmission method according to claim 1 , further comprising:

utilizing the clock signals as the reference clock of the signal output circuit, respectively, to output a set of data, and determining whether a signal receiver correctly receives the data outputted from the signal output circuit to accordingly determine the intermediate signals selected from the clock signals.

6. The signal transmission method according to claim 1 , further comprising:

providing a first selection signal to determine the intermediate signals; and

providing a second selection signal to select one of the intermediate signals as the reference clock.

7. The signal transmission method according to claim 6 , wherein when the first selection signal is a first value, the intermediate signals are a first group of clock signals; when the first selection signal is a second value, the intermediate signals are a second group of clock signals; the first group of clock signals partially overlap with the second group of clock signals.

8. The signal transmission method according to claim 7 , wherein the intermediate signals have adjacent phases.

9. A signal transmitter, comprising:

a clock generator, configured to provide a plurality of clock signals with different phases;

a group selection circuit, configured to select some of the clock signals as a plurality of intermediate signals according to a first selection signal;

a signal output circuit, comprising a multiplexer controlled by a second selection signal to select one of the intermediate signals as a reference clock of the signal output circuit to output data; and

a clock distribution network, configured to transmit the intermediate signals from the group selection circuit to the multiplexer.

10. The signal transmitter according to claim 9 , further comprising:

another signal output circuit, comprising another multiplexer controlled by a third selection signal to select one of the intermediate signals as a reference clock of the another output signal circuit to output data.

11. The signal transmitter according to claim 9 , wherein the group selection circuit comprises a plurality of multiplexers each outputting one of the intermediate signals.

12. The signal transmitter according to claim 9 , wherein the signal output circuit comprises a flip-flop, which captures a data bit that serves as the data outputted from the signal output circuit according to the reference clock as a clock.

13. The signal transmitter according to claim 9 , comprising eight signal output circuits for outputting a data byte, the reference clock of each of the signal output circuits being one of the intermediate signals.

14. The signal transmitter according to claim 9 , wherein when the first selection signal is a first value, the intermediate signals are a first group of clock signals; when the first selection signal is a second value, the intermediate signals are a second group of clock signals; the first group of clock signals partially overlap with the second group of clock signals.

15. The signal transmitter according to claim 9 , wherein the intermediate signals have adjacent phases.

Assignments (2)
MERGER Recorded Jun 8, 2020
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 052871/0833 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2015
From: LIU, HSIAN-FENG; CHEN, CHUN-CHIA; CHANG, KAI-FEI; CHEN, CHAO-AN
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 034651/0078 →