Voltage regulator and semiconductor device
View Patent ↗Provided is a voltage regulator including a clamp circuit capable of protecting a gate of an output transistor without limiting a drivability of the output transistor. The voltage regulator includes a level shift circuit having an input terminal connected to the gate of the output transistor and an output terminal connected to an input of the clamp circuit. The clamp circuit is controlled by an output voltage of the level shift circuit.
1. A voltage regulator, comprising:
a power supply terminal configured to input a power supply voltage;
a reference voltage circuit configured to output a reference voltage;
an output transistor;
an error amplifier circuit configured to amplify and output a difference between a divided voltage and the reference voltage, the divided voltage being obtained by dividing an output voltage output from the output transistor, to thereby control a gate of the output transistor;
a clamp circuit connected between the gate of the output transistor and the power supply terminal, the clamp circuit's operation starting at a predetermined clamp level at which a gate voltage of the output transistor decreases from a withstand voltage of the gate of the output transistor; and
a level shift circuit including at least one transistor and a constant current circuit including one terminal connected to the power supply terminal and connected to the gate of the output transistor and an input terminal of the clamp circuit,
where at least one transistor comprises a first transistor including a gate connected to the input terminal of the level shift circuit, a source connected to another terminal of the constant current circuit and the output terminal of the level shift circuit, and a drain connected to a ground terminal;
wherein the level shift circuit controls the clamp circuit by setting and adjusting the predetermined clamp level with an output voltage of the level shift circuit, thereby protecting a gate of the output transistor and increasing a gate-source voltage of the output transistor, wherein the predetermined clamp level is higher than an absolute value of a threshold voltage of the transistor.
2. The voltage regulator according to claim 1 , wherein the level shift circuit further comprises an impedance element between the constant current circuit and the first transistor.
3. The voltage regulator according to claim 1 , wherein the level shift circuit further comprises:
a second constant current circuit including one terminal connected to the power supply terminal;
a second transistor including a gate connected to the source of the first transistor and a source connected to another terminal of the second constant current circuit;
an n-th constant current circuit, where n is an integer of 2 or more, the n-th constant current circuit including one terminal connected to the power supply terminal; and
an n-th transistor including a gate connected to a source of an (n−1)th transistor and a source connected to another terminal of the n-th constant current circuit and the output terminal of the level shift circuit.
4. The voltage regulator according to claim 2 , wherein the impedance element comprises one of a resistor and a diode-connected transistor.
5. A voltage regulator, comprising:
a power supply terminal configured to input a power supply voltage;
a reference voltage circuit configured to output a reference voltage;
an output transistor;
an error amplifier circuit configured to amplify and output a difference between a divided voltage and the reference voltage, the divided voltage being obtained by dividing an output voltage output from the output transistor, to thereby control a gate of the output transistor;
a clamp circuit connected between the gate of the output transistor and the power supply terminal, the clamp circuit's operation starting at a predetermined clamp level at which a gate voltage of the output transistor decreases from a withstand voltage of the gate of the output transistor; and
a level shift circuit including at least one transistor and a constant current circuit and connected to the gate of the output transistor and an input terminal of the clamp circuit,
wherein the level shift circuit controls the clamp circuit by setting and adjusting the predetermined clamp level with an output voltage of the level shift circuit, thereby protecting a gate of the output transistor and increasing a gate-source voltage of the output transistor, wherein the predetermined clamp level is higher than an absolute value of a threshold voltage of the transistor:
wherein the level shift circuit comprises n transistors, where n is an integer of 2 or more, the n transistors being connected in series between the gate of the output transistor and the power supply terminal and each including a gate and a drain connected to each other,
wherein the gate and the drain of the first transistor of the n transistors are connected to the input terminal of the level shift circuit, and
wherein the gate and the drain of the n-th transistor of the n transistors are connected to the output terminal of the level shift circuit, the n-th transistor including a source connected to the power supply terminal.
6. A semiconductor device, comprising:
an operational amplifier circuit;
an output transistor including a gate connected to an output of the operational amplifier circuit;
a clamp circuit connected to a gate of the output transistor, the clamp circuit's operation starting at a predetermined clamp level at which a gate voltage of the output transistor decreases from a withstand voltage of the gate of the output transistor; and
a level shift circuit including at least one transistor and a constant current circuit and connected to the gate of the output transistor and an input terminal of the clamp circuit,
wherein the level shift circuit controls the clamp circuit by setting and adjusting the predetermined clamp level with an output voltage of the level shift circuit, thereby protecting a gate of the output transistor and increasing a gate-source voltage of the output transistor;
wherein at least one transistor comprises a first transistor including a gate connected to the input terminal of the level shift circuit and a source connected to the constant current circuit and the output terminal of the level shift circuit
wherein the predetermined clamp level is higher than an absolute value of a threshold voltage of the transistor.
7. The semiconductor device according to claim 6 , wherein the level shift circuit further comprises an impedance element between the constant current circuit and the first transistor.
8. The semiconductor device according to claim 6 ,
wherein the level shift circuit comprises n transistors, where n is an integer of 2 or more, the n transistors being connected in series between the gate of the output transistor and a power supply terminal and each including a gate and a drain connected to each other,
wherein the gate and the drain of the first transistor of the n transistors are connected to the input terminal of the level shift circuit, and
wherein the gate and the drain of the n-th transistor of the n transistors are connected to the output terminal of the level shift circuit, the n-th transistor including a source connected to the power supply terminal.
9. The semiconductor device according to claim 6 , wherein
the first constant current circuit including one terminal connected to a power supply terminal; and
the level shift circuit further comprises:
a second constant current circuit including one terminal connected to the power supply terminal;
a second transistor including a gate connected to the source of the first transistor and a source connected to another terminal of the second constant current circuit;
an n-th constant current circuit, where n is an integer of 2 or more, the n-th constant current circuit including one terminal connected to the power supply terminal; and
an n-th transistor including a gate connected to a source of an (n−1)th transistor and a source connected to another terminal of the n-th constant current circuit and the output terminal of the level shift circuit.
10. The semiconductor device according to claim 7 , wherein the impedance element comprises one of a resistor and a diode-connected second transistor.