Validation circuit for reference voltage shifted data

1. A controller comprising:

a high-side circuit referenced to an offset-voltage reference that is offset voltage-wise relative to a ground reference of the controller;

a low-side circuit operable to output a control signal for the high-side circuit, wherein the control signal is referenced to the ground reference;

a level-shift circuit configured to output a shifted signal to the high-side circuit that is referenced to the offset-voltage reference and based on the control signal;

a data-validation circuit configured to receive the shifted signal, determine a first value of the shifted signal at a first instant, determine a second value of the shifted signal at a second instant different in time from the first instant, and validate the shifted signal based on a determination that the first value and the second value correspond.

2. The controller in accordance with claim 1 , wherein the high-side circuit is operable to apply a high-side voltage to a high-side terminal of a load, wherein the high-side circuit is referenced to the high-side terminal.

3. The controller in accordance with claim 1 , wherein the low-side circuit is also operable to apply a low-side voltage to a low-side terminal of the load.

4. The controller in accordance with claim 1 , wherein the control signal output by the low-side circuit at the second instant is characterized as an ones-complement of the control signal output by the low-side circuit at the first instant, whereby the first value and the second value correspond when the second value equals an ones-complement of the first value.

5. The controller in accordance with claim 1 , wherein the data-validation circuit includes a first data-latch configured to capture the first value at the first instant, a second data-latch configured to capture the second value at the second instant, and an exclusive-or-gate configured to indicate if the first value and the second value correspond.

6. The controller in accordance with claim 5 , wherein the control signal includes a plurality of data-bits output in parallel, the data-validation circuit includes a plurality of exclusive-or gates configured to compare the first value and the second value of each of the data-bits, and the data-validation circuit includes a first and-gate configured to output a Data-Loaded-and-Stored-Correctly (DLSC) signal when the first value and the second value of all of the data-bits correspond.

7. The controller in accordance with claim 6 , wherein the level-shift circuit is further configured to shift the DLSC from the offset-voltage reference to the ground reference for use by the low-side circuit.

8. The controller in accordance with claim 6 , wherein the data-validation circuit includes a protected register configured to capture the outputs of the first data latch and the second data latch for each of the data-bits in response to the DLSC signal.

9. The controller in accordance with claim 8 , wherein the data-validation circuit includes a second and-gate configured to output a Protected-Register-data-OK (PROK) signal when the outputs of the first data latch and the second data latch of all of the data-bits captured by the protected register correspond.

10. The controller in accordance with claim 9 , wherein the level-shift circuit is further configured to shift the PROK from the offset-voltage reference to the ground reference for use by the low-side circuit.