IP Library Granted Patent US 9,601,655
Granted Patent B2
US 9,601,655 · App. 14/591,772 · Granted Mar 21, 2017

Optoelectronic device and method for manufacturing the same

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Quick Facts
Patent No.
US 9,601,655
App. No.
14/591,772
Granted
Mar 21, 2017
Kind
B2
Abstract

An optoelectronic device comprises a semiconductor stack, wherein the semiconductor stack comprises a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; an electrode formed on the second semiconductor layer, wherein the first electrode further comprises a reflective layer; and an insulative layer formed on the second semiconductor layer, and a space formed between the first electrode and the insulative layer.

Claims (21)

1. A method of fabricating an optoelectronic device, the method comprising:

providing a semiconductor stack, wherein the semiconductor stack further comprises: a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer;

etching the semiconductor stack to expose a portion of the first semiconductor layer;

forming an insulative layer on the semiconductor stack;

forming a photoresist layer on the insulative layer;

etching the insulative layer in accordance with the photoresist layer to expose a portion of the first semiconductor layer and a portion of the second semiconductor layer;

forming a first metal layer, wherein a first portion of the first metal layer is formed on the portion of the second semiconductor layer and a second portion of the first metal layer is formed on the photoresist layer, wherein a space is formed between the first portion of the first metal layer and the insulative layer; and

removing the photoresist layer and the second portion of the first metal layer.

2. A method of claim 1 , wherein the etching comprising a side etching of the insulating layer to form the space.

3. A method of claim 1 , further comprising a first height between a first top surface of the first portion of the first metal layer and a first surface the second semiconductor layer,

a second height between a second top surface of the first insulative layer and the first surface of the second semiconductor layer,

wherein the first height and the second height are substantially equal or a difference between the first height and the second height is less than 1 μm.

4. A method of claim 1 , further comprising forming a second metal layer on the first portion of the first metal layer, wherein the space is between a first side surface of the insulative layer and a second side surface of the first portion of the first metal layer, wherein the second metal layer fills the space, wherein the second metal layer comprises a third side surface, and wherein the third side surface is aligned with the first side surface.

5. A method of claim 4 , further comprising a third portion of the first metal layer on the first semiconductor layer, and forming a third metal layer on the third portion of the first metal layer.

6. A method of claim 5 , further comprising a first shortest distance between a top surface of the second metal layer and a bottom surface of the first semiconductor layer, and

a second shortest distance between a top surface of the third metal layer and the bottom surface of the first semiconductor layer, and

wherein a difference between the first shortest distance and the second shortest distance is less than 1 μm.

7. A method of claim 1 , wherein the space is less than 3 μm.

8. A method of claim 5 , further comprising providing a sub-mount electrically connecting to the second metal layer and the third metal layer.

9. A method of claim 1 , wherein an undercut is formed in the insulative layer after etching in accordance with the photoresist layer.

10. A method of claim 1 , further comprises etching the photoresist layer and the first metal layer on the photoresist layer after forming a first metal layer on the second semiconductor layer and the photoresist layer.

Assignments (2)
CHANGE OF NAME Recorded Feb 18, 2026
From: EPISTAR CORPORATION
To: ENNOSTAR CORPORATION
Reel/Frame 075171/0402 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2015
From: WANG, JIA-KUEN; CHEN, CHAO-HSING
To: EPISTAR CORPORATION
Reel/Frame 034668/0658 →