Switched capacitor DC-DC converter with reduced in-rush current and fault protection
To reduce in-rush currents into a switched capacitor DC/DC converter and detect voltage and current faults, a converter controller is housed along with a current limit series transistor and fault detection circuitry. The series transistor is controlled to limit the in-rush current to a predetermined maximum level during start-up. If the duration of the current limit level, or the time for Vout to achieve a target voltage, exceeds a first threshold time, a first fault detector in the package shuts off the series transistor. During steady state operation, if the input current reaches the limit for a second threshold time or if Vout extends outside a certain range for the second threshold time, a second fault detector in the package shuts off the series transistor.
1. A circuit for controlling a switched capacitor DC/DC converter to generate an output voltage Vout comprising:
a controller circuit for generating control signals for controlling switches in the switched capacitor DC/DC converter to generate Vout;
an input terminal for an input voltage Vin 1 ;
an input current sensor for generating an input current signal corresponding to an input current;
a current limit circuit coupled to the input current sensor for detecting when the input current has reached a current limit level and for controlling in-rush current into the converter so as not to exceed the current limit level, wherein the current limit circuit controls the in-rush current so as not to exceed a predetermined maximum current level;
a series transistor coupled between the input terminal and the converter;
a series transistor controller for controlling the series transistor to limit the in-rush current into the converter to the current limit level during start-up when Vin 1 is applied to the input terminal;
a fault detection circuit comprising:
a first fault circuit for detecting whether there is an input current fault or a Vout fault during a start-up phase of the circuit and for turning off the series transistor if a fault is detected during the start-up phase; and
a second fault circuit for detecting whether there is an input current fault or a Vout fault during a steady state phase of the circuit and for turning off the series transistor if a fault is detected during the steady state phase.
2. The circuit of claim 1 wherein the series transistor controller is connected in a loop with the series transistor, the current limit circuit, and the input current sensor.
3. The circuit of claim 1 wherein the first fault circuit comprises a first timer, and the second fault circuit comprises a second timer.
4. The circuit of claim 1 wherein, except for one or more capacitors, the controller circuit, the series transistor, the current limit circuit, the series transistor controller, the first fault circuit, and the second fault circuit are housed in a single package.
5. The circuit of claim 3 wherein the first timer signals a fault after a first time limit if the input current is at the current limit level at the time of the first time limit, signaling that there is an input current fault, and
wherein the first timer also signals a fault after the first time limit if Vout is not within a target range at the time of the first circuit limit, signaling that there is a Vout fault.
6. The circuit of claim 3 wherein the first timer is started at an initiation of start-up.
7. The circuit of claim 3 wherein the first timer comprises a first switch coupling a first current source to a timer capacitor, where a capacitor voltage is compared to a first reference voltage by a first comparator.
8. The circuit of claim 5 wherein the second timer is started when the input current reaches the current limit level, wherein the second timer signals that there is an input current fault if the input current remains at the current limit level for a second time limit, and
wherein the second timer is also started when Vout is not within the target range, wherein the second timer signals that there is a Vout fault if Vout remains outside the target range for the second time limit.
9. The circuit of claim 7 wherein the second timer comprises a second switch coupling a second current source to the timer capacitor, where the capacitor voltage is compared to a second reference voltage by a second comparator.
10. The circuit of claim 7 wherein the timer capacitor is reset when there is no fault condition.
11. The circuit of claim 8 wherein the first time limit is different from the second time limit.
12. The circuit of claim 8 further comprising a voltage generator coupled to receive the input voltage Vin 1 , the voltage generator generating a first voltage greater than Vin 1 /N and generating a second voltage lower than Vin 1 /N, wherein N equals Vin 1 /Vout in steady state and the first voltage and the second voltage define the target range of Vout.
13. The circuit of claim 12 wherein Vout is compared to the first voltage and the second voltage by a first comparator and a second comparator to determine if Vout is within the target range.
14. A method for controlling a switched capacitor DC/DC converter to generate an output voltage Vout comprising:
receiving, at an input terminal, an input voltage Vin 1 for powering the switched capacitor DC/DC converter;
generating, by a controller circuit, control signals for controlling switches in the converter to generate Vout;
sensing an input current, by an input current sensor, and generating an input current signal corresponding to an input current;
generating a current limit signal, by a current limit circuit, coupled to the input current sensor for controlling in-rush current into the converter so as not to exceed a current limit level;
limiting the in-rush current to the current limit level by a series transistor coupled between the input terminal and the converter,
wherein the series transistor is controlled by the current limit circuit to limit the in-rush current into the converter to the current limit level during start-up when Vin 1 is applied to the input terminal;
detecting, by a first fault circuit, whether there is an input current fault or a Vout fault during a start-up phase of the circuit and turning off the series transistor if a fault is detected during the start-up phase; and
detecting, by a second fault circuit, whether there is an input current fault or a Vout fault during a steady state phase of the circuit and turning off the series transistor if a fault is detected during the steady state phase.
15. The method of claim 14 wherein the first fault circuit comprises a first timer, and wherein the second fault circuit comprises a second timer.
16. The method of claim 14 further comprising generating, by a voltage generator coupled to receive the input voltage Vin 1 , a first voltage greater than a target Vout and generating a second voltage lower than the target Vout, wherein the first voltage and the second voltage define the target range of Vout.
17. The method of claim 15 wherein the first timer signals a fault after a first time limit if the input current is at the current limit level at the time of the first time limit, signaling that there is an input current fault, and
wherein the first timer also signals a fault after the first time limit if Vout is not within a target range at the time of the first circuit limit, signaling that there is a Vout fault.
18. The method of claim 15 wherein the first timer is started at an initiation of start-up.
19. The method of claim 15 wherein the first timer comprises a first switch coupling a first current source to a timer capacitor, where a capacitor voltage is compared to a first reference voltage by a first comparator.
20. The method of claim 17 wherein the second timer is started when the input current reaches the current limit level, wherein the second timer signals that there is an input current fault if the input current remains at the current limit level for a second time limit, and
wherein the second timer is also started when Vout is not within the target range, wherein the second timer signals that there is a Vout fault if Vout remains outside the target range for the second time limit.
21. The method of claim 19 wherein the second timer comprises a second switch coupling a second current source to the timer capacitor, where the capacitor voltage is compared to a second reference voltage by a second comparator.
22. The method of claim 20 wherein the first time limit is different from the second time limit.
23. The method of claim 21 wherein the capacitor is reset when there is no fault condition.