LOW CAPACITANCE DISPLAY ADDRESS SELECTOR ARCHITECTURE
This disclosure provides display-related systems, methods, and apparatus. A display apparatus can include an array of display elements and an address-selector architecture for addressing and loading data into the array of display elements. The address-selector architecture can include a plurality of bank drive interconnects that can provide write enable voltages. Each of a plurality of scan-line interconnects, where each scan-line interconnect is coupled to one row of display elements, is selectively electrically connected to one bank drive interconnect via a transistor. The scan-line interconnects and their corresponding transistors are grouped into a number of row-banks, where the row-banks can include unequal number of scan-line interconnects. The gate terminals of the transistors in each row-bank are connected to a bank-control interconnect. A bank control interconnect driver provides voltages to the bank-control interconnects for selectively turning the transistors in each bank ON and OFF.
1 . An apparatus comprising:
an array of display elements arranged in rows and columns;
a plurality of scan-line interconnects arranged in row-banks, each of the plurality of scan-line interconnects coupled to one row of display elements;
a plurality of bank drive interconnects, each of the plurality of bank drive interconnects capable of carrying a write enable voltage to one scan-line interconnect in at least one row-bank;
a write enable voltage driver coupled to the plurality of bank drive interconnects and capable of providing write enable voltages to each of the plurality of bank drive interconnects;
a plurality of row-enable transistors, wherein one of the source and drain terminals of each of the plurality of row-enable transistors is coupled to one of the plurality of scan-line interconnects, and the other terminal is coupled to one of the plurality of bank drive interconnects;
a plurality of bank control interconnects, each of the plurality of bank control interconnects coupled to the gate terminals of the row-enable transistors associated with scan-line interconnects of a corresponding row-bank; and
a bank control interconnect driver coupled to the plurality of bank control interconnects capable of providing control voltages to each of the plurality of bank control interconnects;
wherein the number of scan-line interconnects in a first row-bank located a first distance from the write-enable voltage driver is greater than a number of scan-line interconnects in a second row-bank of scan-line interconnects located a second distance, farther from the write-enable voltage driver.
2 . The apparatus of claim 1 , wherein the number of scan-line interconnects in each row-bank is based in part on a load parameter associated with a bank control interconnect coupled to the row-enable transistors associated with the respective row-banks.
3 . The apparatus of claim 1 , wherein the size of a first of the row-enable transistors located a first distance from the bank control interconnect driver is greater than the size of a second of the row-enable transistors located a second distance, nearer from the bank control interconnect driver.
4 . The apparatus of claim 1 , wherein the sizes of the plurality of row-enable transistors are substantially the same.
5 . The apparatus of claim 1 , wherein the row-enable transistor located farthest from the write-enable voltage driver is coupled to a bank drive interconnect that is coupled to a fewer number of other row-enable transistors than at least one other bank drive interconnect.
6 . The apparatus of claim 1 , wherein propagation delays of control voltages provided by the bank control interconnect driver over the plurality of bank control interconnects are substantially equal.
7 . The apparatus of claim 1 , wherein the number of bank drive interconnects is equal to the number of row-enable transistors in the largest row-bank of scan-line interconnects.
8 . The apparatus of claim 1 , wherein each of the bank drive interconnects terminates at the farthest row-enable transistor coupled to the bank drive interconnect.
9 . The apparatus of claim 1 , wherein the array of display elements are located within a display area on a substrate, and wherein the plurality of bank drive interconnects and the plurality of bank control interconnects are located on the substrate outside of the display area.
10 . The apparatus of claim 1 , wherein RC time constants associated with the plurality of row-control interconnect are substantially equal.
11 . The apparatus of claim 1 , further comprising:
a display;
a processor capable of communicating with the display, the processor being capable of processing image data; and
a memory device capable of communicating with the processor.
12 . The apparatus of claim 11 , further comprising:
a driver circuit capable of sending at least one signal to the display; and
a controller capable of sending at least a portion of the image data to the driver circuit.
13 . The apparatus of claim 11 , further comprising:
an image source module capable of sending the image data to the processor, wherein the image source module includes at least one of a receiver, transceiver, and transmitter.
14 . The apparatus of claim 11 , further comprising:
an input device capable of receiving input data and communicating the input data to the processor.
15 . An apparatus comprising:
an array of display elements arranged in rows and columns;
a plurality of scan-line interconnects arranged in row-banks, each of the plurality of scan-line interconnects coupled to one row of display elements from the array of display elements;
a plurality of bank drive interconnects, each of the plurality of bank drive interconnects capable of carrying a write enable voltage to one scan-line interconnect in at least one row-bank;
a write enable voltage driver coupled to the plurality of bank drive interconnects and capable of providing write enable voltages to each of the plurality of bank drive interconnects;
a plurality of row-enable transistors, wherein one of the source and drain terminals of each of the plurality of row-enable transistors is coupled to one of the plurality of scan-line interconnects, and the other of the source and drain terminals of each of the plurality of row-enable transistors is coupled to one of the plurality of bank drive interconnects;
a plurality of bank control interconnects, each of the plurality of bank control interconnects coupled to the gate terminals of the row-enable transistors associated with scan-line interconnects arranged in a corresponding row-bank; and
a bank control interconnect driver coupled to the plurality of bank control interconnects capable of providing control voltages to each of the plurality of bank control interconnects;
wherein the size of a first of the row-enable transistors located a first distance from the bank control interconnect driver is greater than the size of a second of the row-enable transistors located a second distance, nearer from the bank control interconnect driver.
16 . The apparatus of claim 15 , wherein the number of scan-line interconnects in a first row-bank located a first distance from the write-enable voltage driver is greater than a number of scan-line interconnects in a second row-bank of scan-line interconnects located a second distance, greater than the first distance, from the write-enable voltage driver.
17 . The apparatus of claim 15 , wherein each of the bank drive interconnects terminates at the farthest row-enable transistor coupled to the bank drive interconnect.
18 . An apparatus comprising:
an array of display elements arranged in rows and columns;
a plurality of scan-line interconnects arranged in row-banks, each of the plurality of scan-line interconnects coupled to one row of display elements from the array of display elements;
a plurality of bank drive interconnects, each of the plurality of bank drive interconnects capable of carrying a write enable voltage to one scan-line interconnect in at least one row-bank;
a write enable voltage driver coupled to the plurality of bank drive interconnects and capable of providing write enable voltages to each of the plurality of bank drive interconnects;
a plurality of row-enable transistors, wherein one of the source and drain terminals of each of the plurality of row-enable transistors is coupled to one of the plurality of scan-line interconnects, and the other of the source and drain terminals of each of the plurality of row-enable transistors is coupled to one of the plurality of bank drive interconnects;
a plurality of bank control interconnects, each of the plurality of bank control interconnects coupled to the gate terminals of the row-enable transistors associated with the scan-line interconnects of a corresponding row-bank; and
a bank control interconnect driver coupled to the plurality of bank control interconnects capable of providing control voltages to each of the plurality of bank control interconnects;
wherein each of the bank drive interconnects terminates at the farthest row-enable transistor coupled to the bank drive interconnect.
19 . The apparatus of claim 18 , wherein the number of scan-line interconnects in a first row-bank located a first distance from the write-enable voltage driver is greater than a number of scan-line interconnects in a second row-bank of scan-line interconnects located a second distance, greater than the first distance, from the write-enable voltage driver.
20 . The apparatus of claim 18 , wherein the size of a first of the row-enable transistors located a first distance from the bank control interconnect driver is greater than the size of a second of the row-enable transistors located a second distance from the bank control interconnect driver, wherein the first distance is greater than the second distance.