Multi-core processor for optimized power consumption in a security and home automation system

1. A security and home automation system for optimizing power consumption, comprising:

a multi-core processor having a first core and a second core, the first core partitioned from the second core to form an asymmetric multi-core processor, wherein:

the first core is a master core assigned to execute a real time operating system (RTOS) and configured to periodically transition between a partial sleep state and an awake state during a power shortage condition, the first core configured to determine through self-monitoring when to periodically transition between the partial sleep state and the awake state during the power shortage condition, and

the second core is a slave core assigned to execute a full-blown operating system (OS) and configured to enter a deep sleep state during the power shortage condition.

2. The security and home automation system of claim 1 , further comprising a memory shared between the first core and the second core, the memory configured to allow the first core and the second core to communicate with each other, the first core and the second core each configured to send data to the memory and issue an interrupt upon sending the data to the memory indicating an availability of the data, wherein the memory is an internal memory of the multi-core processor.

3. The security and home automation system of claim 1 , further comprising a power management module having a power management interface in communication with the first core and the second core, the power management module configured to detect the power shortage condition.

4. The security and home automation system of claim 3 , the power management module configured to issue a sleep request and a wakeup request.

5. The security and home automation system of claim 1 , the first core configured to:

determine, through a power management module, when to issue a sleep request for the second core;

send a request to the second core to enter one of the awake state and the deep sleep state; and

determine if any pending tasks of the RTOS are to be performed prior to entering the partial sleep state.

6. The security and home automation system of claim 1 , the second core configured to:

receive and acknowledge a request from the first core to enter one of the awake state and the deep sleep state;

determine if any pending tasks of the full-blown OS are to be performed prior to entering the deep sleep state; and

enter the awake state during the power shortage condition upon receipt of the request to enter the awake state.

7. The security and home automation system of claim 1 , further comprising a level 1 (L1) cache, a level 2 (L2) cache and an internal random access memory (RAM), the first core configured to transfer and lock data of the RTOS into the L1 cache, the L2 cache, and the internal RAM.

8. The security and home automation system of claim 1 , wherein the full-blown OS is one of a Windows or Linux operating system, and wherein the full-blown OS executes a plurality of lifestyle applications and the RTOS executes a plurality of life safety applications.

9. A computer-implemented method for optimizing power consumption in an intrusion detection and home automation system using a processor device, comprising:

partitioning a first core from a second core in a multi-core processor to form an asymmetric multi-core processor, wherein the first core is a master core executing a real time operating system (RTOS) and the second core is slave core executing a full-blown operating sy stem (OS);

periodically transitioning the first core between a partial sleep state and an awake state during a power shortage condition, wherein the first core determines through self-monitoring when to periodically transition between the partial sleep state and the awake state during the power shortage condition; and

placing the second core in a deep sleep state during the power shortage condition.

10. The method of claim 9 , further comprising:

sharing a memory between the first core and the second core for allowing the first core and the second core to communicate with each other;

issuing an interrupt upon sending data to the memory by the first core indicating availability of data; and

triggering a wakeup request for the second core using the interrupt.

11. The method of claim 9 , further comprising detecting the power shortage condition by a power management module having a power management interface in communication with the first core and the second core.

12. The method of claim 11 , further comprising issuing one of a sleep request and a wakeup request by the power management module.

13. The method of claim 9 , further comprising:

determining by the first core when to issue a sleep request for the second core;

sending to the second core one of a wakeup request to enter the awake state and the sleep request to enter the deep sleep state; and

determining if any pending tasks are to be performed prior to entering one of the partial sleep state by the first core and entering the deep sleep state by the second core.

14. The method of claim 9 , further comprising:

receiving from the first core and acknowledging by the second core one of a wakeup request to enter the awake state and a sleep request to enter the deep sleep state; and

entering the awake state by the second core during the power shortage condition upon receipt of the wakeup request.

15. The method of claim 9 , further comprising transferring and locking data of the RTOS by the first core into a level 1 (L1) cache, a level 2 (L2) cache, and an internal random access memory (RAM).

16. The method of claim 9 , further comprising executing a plurality of lifestyle applications by the full-blown OS and executing a plurality of life safety applications by the RTOS, wherein the full-blown OS is one of a Windows operating system and a Linux operating system.

17. A system for optimizing power consumption during a power shortage condition, comprising:

a multi-core processor having a first core partitioned from a second core;

an internal memory shared between the first core and the second core, the internal memory configured to allow the first core and the second core to communicate with each other; and

a power management module having a power management interface, the power management module controlled by the first core and in communication with the second core, the power management module configured to detect the power shortage condition and issue a sleep request and a wakeup request; wherein:

the first core is a master core assigned to execute a real time operating system (RTOS) and configured to periodically transition between a partial sleep state and an awake state, the first core configured to determine through self-monitoring when to periodically transition between the partial sleep state and the awake state during the power shortage condition; and

the second core includes a plurality of slave cores assigned to execute a full-blown operating system (OS) and configured to enter a deep sleep state during the power shortage condition, wherein the full-blown OS is one of a Windows operating system and a Linux operating system, and the full-blown OS executes a plurality of lifestyle applications and the RTOS executes a plurality of life safety applications.

18. The system of claim 17 , wherein the first core and the second core are each configured to send data to the internal memory, and the first core is configured to issue an interrupt upon sending the data to the internal memory indicating availability of data when the second core is in the deep sleep state.

19. The system of claim 17 , wherein the first core is configured to:

determine when to issue the sleep request for the second core;

send to the second core one of the wakeup request to enter the awake state and the sleep request to enter the deep sleep state; and

determine if any pending tasks of the RTOS are to be performed prior to entering the partial sleep state.

20. The system of claim 17 , further comprising a level 1 (L1) cache, a level 2 (L2) cache and an internal random access memory (RAM), the first core configured to transfer and lock data of the RTOS into the L1 cache, the L2 cache, and the internal RAM.