IP Library Granted Patent US 9,735,112
Granted Patent B2
US 9,735,112 · App. 14/593,642 · Granted Aug 15, 2017

Isolation between semiconductor components

Inventors: John Constantino (Morgan Hill, CA); Timwah Luk (Falmouth, ME); Ahmad Ashrafzadeh (Morgan Hill, CA); Robert L. Krause (San Jose, CA); Etan Shacham (Cupertino, CA); Maria Clemens Ypil Quinones (Cebu, PH); Janusz Bryzek (Oakland, CA); Chung-Lin Wu (San Jose, CA)
Assignee: Fairchild Semiconductor Corporation
H01L23/538H01L23/49531H01L23/49537H01L23/49541H01L23/49575H01L23/49589H01L23/66H01L27/06H01L28/40H01L2224/0603H01L2224/16145H01L2224/32145H01L2224/48091H01L2224/48137H01L2224/48247H01L2224/73257H01L2224/73265H01L2924/13055H01L2924/181
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Quick Facts
Patent No.
US 9,735,112
App. No.
14/593,642
Granted
Aug 15, 2017
Kind
B2
Abstract

In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to the first semiconductor die and the second semiconductor die. The capacitive isolation circuit may be disposed outside of the first semiconductor die and the second semiconductor die. The first semiconductor die, the second semiconductor die, and the capacitive circuit may be included in a molding of a semiconductor package.

Claims (44)

1. An apparatus comprising:

a first lead frame portion;

a second lead frame portion;

a first semiconductor die, the first semiconductor die being in a flip-chip configuration;

a second semiconductor die; and

an isolation substrate bridge including a dielectric substrate, the dielectric substrate having a first surface, a second surface, a first end portion, and a second end portion, the first end portion being coupled to the first lead frame portion, the second end portion being coupled to the second lead frame portion, the isolation substrate bridge being disposed outside of the first semiconductor die and the second semiconductor die,

the first semiconductor die, the second semiconductor die, and the isolation substrate bridge being included in a molding of a semiconductor package, the first semiconductor die being coupled to the first surface of the dielectric substrate via a conductive component, the second semiconductor die being coupled to the first surface of the dielectric substrate,

the isolation substrate bridge including a pair of conductive transmission lines disposed on the second surface of the dielectric substrate, the pair of conductive transmission lines being separated from the conductive component by a thickness of the isolation substrate bridge.

2. The apparatus of claim 1 , wherein the isolation substrate bridge is configured to transmit data between the first semiconductor die and the second semiconductor die via the pair of conductive transmission lines.

3. The apparatus of claim 1 , wherein the dielectric substrate includes one of a glass material and a ceramic material.

4. The apparatus of claim 1 , wherein the isolation substrate bridge includes a dielectric thickness that provides a distance through insulation equal to or greater than 0.1 mm.

5. The apparatus of claim 1 , wherein the isolation substrate bridge defines a distance through insulation that is at least twice a thickness of the isolation substrate bridge, the twice the thickness being greater than or equal to a minimum distance between the first semiconductor die and the second semiconductor die.

6. The apparatus of claim 1 , wherein the pair of conductive transmission lines define a differential communication channel for communicating between the first semiconductor die and the second semiconductor die.

7. The apparatus of claim 1 , wherein at least one of the first semiconductor die and the second semiconductor die includes a top conductive layer and a bottom conductive layer, wherein the isolation substrate bridge is formed outside the top conductive layer and the bottom conductive layer.

8. An apparatus comprising:

a first lead frame;

a second lead frame, the second lead frame being separated from the first lead frame by a distance;

a first semiconductor die;

a second semiconductor die;

an isolation substrate bridge including a dielectric substrate and a pair of conductive transmission lines, the dielectric substrate having a first surface, a second surface, a first end portion, and a second end portion, the first end portion being coupled to the first lead frame, the second end portion being coupled to the second lead frame,

the first semiconductor die and the second semiconductor die being coupled to the first surface of the dielectric substrate, the pair of conductive transmission lines being coupled to the second surface of the dielectric substrate; and

a conductive component coupled to the second lead frame and the second semiconductor die, the conductive component extending along a portion of the second surface between the second lead frame and the second semiconductor die,

the isolation substrate bridge defining a distance through insulation that is at least twice a thickness of the isolation substrate bridge, the twice the thickness being greater than or equal to a distance between the first semiconductor die and the second semiconductor die.

9. An apparatus comprising:

a first semiconductor die;

a second semiconductor die, the first semiconductor die being in a flip-chip configuration; and

an isolation substrate bridge coupled to the first semiconductor die and the second semiconductor die, the isolation substrate bridge configured to support communication between the first semiconductor die and the second semiconductor die;

a molding compound disposed on a first surface of the isolation substrate bridge such that the molding compound encloses the first semiconductor die and the second semiconductor die;

at least one conductive transmission line coupled to a second surface of the isolation substrate bride; and

a plurality of stacks disposed on an end portion of the isolation substrate bridge, each stack of the plurality of stacks being coupled to a different terminal of the first semiconductor die via a separate trace, each stack of the plurality of stacks having a portion that protrudes outward from an outer surface of the molding compound.

10. The apparatus of claim 9 , wherein the isolation substrate bridge includes a differential communication channel for communicating between the first semiconductor die and the second semiconductor die.

11. The apparatus of claim 9 , wherein at least one of the first semiconductor die and the second semiconductor die includes a top conductive layer and a bottom conductive layer, wherein the isolation substrate bridge is formed outside the top conductive layer and the bottom conductive layer.

12. The apparatus of claim 1 , further comprising:

a first conductive component coupled to the first lead frame portion and the first semiconductor die, the first conductive component having a portion that is disposed between the first lead frame portion and the first end portion of the isolation substrate bridge, the first conductive component extending along a portion of the second surface of the dielectric substrate between the first lead frame portion and the first semiconductor die;

a second conductive component coupled to the second lead frame portion and the second semiconductor die, the second conductive component having a portion that is disposed between the second lead frame portion and the second end portion of the isolation substrate bridge, the second conductive component extending along a portion of the second surface of the dielectric substrate between the second lead frame portion and the second semiconductor die.

13. The apparatus of claim 1 , wherein the isolation substrate bridge includes a secondary pair of conductive transmission lines disposed on the second surface of the dielectric substrate, wherein the pair of conducive transmission lines and the secondary pair of conductive transmission lines define a bi-directional communication channel.

14. The apparatus of claim 1 , wherein the conductive component is a first conductive bump, and the first semiconductor die is coupled to the isolation substrate bridge with the first conductive bump and a second conductive bump, the first conductive bump disposed apart from the second conductive bump.

15. The apparatus of claim 8 , further comprising:

a secondary conductive component coupled to the first lead frame and the first semiconductor die, the secondary conductive component extending along a portion of the second surface between the first lead frame and the first semiconductor die.

16. The apparatus of claim 8 , wherein the second semiconductor die is coupled to the isolation substrate bridge via a first conductive bump and a second conductive bump, wherein the conductive component is coupled to the second conductive bump and extends along the portion of the second surface to the second lead frame.

17. The apparatus of claim 8 , wherein the first semiconductor die and the second semiconductor die are disposed between the first lead frame and the second lead frame.

18. The apparatus of claim 8 , wherein the first surface of the dielectric substrate includes a first conductive plate and a second conductive plate, the first conductive plate being vertically aligned with a first end portion of the pair of conductive transmission lines, the second conductive plate being vertically aligned with a second end portion of the pair of conductive transmission lines.

19. The apparatus of claim 9 , further comprising a capacitive plate coupled to the first semiconductor die and disposed on the first surface of the isolation substrate bridge, the at least one conductive transmission line being separated from the capacitive plate by a thickness of the isolation substrate bridge.

20. The apparatus of claim 19 , wherein the second semiconductor die is communicatively coupled to the at least one conductive transmission line through a conductive via that extends through the thickness of the isolation substrate bridge.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 9, 2015
From: CONSTANTINO, JOHN; LUK, TIMWAH; ASHRAFZADEH, AHMAD; KRAUSE, ROBERT L.; SHACHAM, ETAN; QUINONES, MARIE CLEMENS YPIL; BRYZEK, JANUSZ; WU, CHUNG-LIN
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 034675/0813 →
Continuity (2)
Provisional Application 61926030 · Jan 10, 2014
Related Publication 20150200162A1 · Jul 16, 2015