Amplifier circuit
View Patent ↗Provided is an amplifier circuit including an NMOS transistor having a low drain breakdown voltage and an NMOS transistor having a high drain breakdown voltage connected in series thereto, and capable of preventing breakdown of a drain of the NMOS transistor having a low drain breakdown voltage. A clamp circuit configured to limit a drain voltage of the NMOS transistor having a low drain breakdown voltage is connected to the drain thereof.
1. An amplifier circuit configured to amplify a signal input to an input terminal and to output the amplified signal to an output terminal,
the amplifier circuit comprising:
a first transistor including a gate directly connected to the input terminal;
a second transistor including a drain connected to the output terminal and a source connected to a drain of the first transistor, the second transistor having a drain breakdown voltage higher than a drain breakdown voltage of the first transistor and being always in an operating state; and
a clamp circuit connected between the drain of the first transistor and a power supply, and configured to limit a drain voltage of the first transistor.
2. An amplifier circuit according to claim 1 , wherein the second transistor comprises an enhancement transistor including a gate connected to a constant voltage circuit.
3. An amplifier circuit configured to amplify a signal input to an input terminal and to output the amplified signal to an output terminal,
the amplifier circuit comprising:
a first transistor including a gate connected to the input terminal;
a second transistor including a drain connected to the output terminal and a source connected to a drain of the first transistor, the second transistor having a drain breakdown voltage higher than a drain breakdown voltage of the first transistor and being always in an operating state; and
a clamp circuit connected to the drain of the first transistor, and configured to limit a drain voltage of the first transistor;
wherein the second transistor comprises a depletion transistor.
4. An amplifier circuit according to claim 3 , wherein the second transistor includes a gate connected to a constant voltage circuit.
5. An amplifier circuit according to claim 3 , wherein the second transistor includes a gate connected to the input terminal.
6. An amplifier circuit according to claim 1 , wherein the clamp circuit comprises a plurality of diode-connected transistors connected in series.
7. An amplifier circuit according to claim 1 , wherein the clamp circuit comprises a transistor including a gate connected to a constant voltage circuit.
8. An amplifier circuit according to claim 1 , wherein the clamp circuit comprises:
a transistor including a gate connected to a constant voltage circuit; and
a plurality of diode-connected transistors,
the transistor and the plurality of diode-connected transistors being connected in series.
9. An amplifier circuit according to claim 1 , wherein the clamp circuit comprises a transistor including a gate and a source both connected to the drain of the first transistor and a drain connected to a constant voltage circuit.
10. An amplifier circuit configured to amplify a signal input to an input terminal and to output the amplified signal to an output terminal,
the amplifier circuit comprising:
a first transistor including a gate connected to a constant voltage circuit, a drain connected to the output terminal, and a source connected to a power supply terminal;
a second transistor including a gate connected to the input terminal, a drain connected to a ground terminal, and a source connected to the output terminal, the second transistor having a drain breakdown voltage higher than a drain breakdown voltage of the first transistor; and
a clamp circuit comprising a transistor including a gate and a source both connected to the drain of the first transistor and a drain connected to the input terminal, the clamp circuit being configured to limit a drain voltage of the first transistor.
11. An amplifier circuit according to claim 3 , wherein the clamp circuit comprises a plurality of diode-connected transistors connected in series.
12. An amplifier circuit according to claim 3 , wherein the clamp circuit comprises a transistor including a gate connected to a constant voltage circuit.
13. An amplifier circuit according to claim 3 , wherein the clamp circuit comprises:
a transistor including a gate connected to a constant voltage circuit; and
a plurality of diode-connected transistors,
the transistor and the plurality of diode-connected transistors being connected in series.
14. An amplifier circuit according to claim 3 , wherein the clamp circuit comprises a transistor including a gate and a source both connected to the drain of the first transistor and a drain connected to a constant voltage circuit.