Silicon wafers with suppressed minority carrier lifetime degradation
View Patent ↗Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates.
1. A silicon wafer comprising boron, boron being present in the wafer in a concentration of at least about 10 13 atoms/cm 3 , the minority carrier lifetime degradation of the wafer related to a degradation defect comprising a fast-diffusing component and a dimeric oxygen-containing component being suppressed by:
heating the silicon wafer to a temperature T 1 which is sufficient to nucleate nano-precipitates of the fast-diffusing component of the degradation defect;
cooling the silicon wafer from T 1 to a temperature T 2 at a cooling rate R 1 of at least about 100° C./sec; and
cooling the silicon wafer from T 2 to a temperature T 3 at a cooling rate R 2 while illuminating the wafer, the ratio of R 1 to R 2 being at least about 2:1.
2. A silicon wafer as set forth in claim 1 wherein the ratio of R 1 to R 2 is at least about 10:1.
3. A silicon wafer as set forth in claim 1 wherein the ratio of R 1 to R 2 is at least about 20:1.
4. A silicon wafer as set forth in claim 1 wherein the ratio of R 1 to R 2 is at least about 50:1.
5. A silicon wafer as set forth in claim 1 wherein the pre-existing nano-precipitates dissolved in the heating step are composed of boron, copper, nickel or combinations thereof.
6. A silicon wafer as set forth in claim 1 wherein the pre-existing nano-precipitates dissolved in the heating step are composed of boron.
7. A silicon wafer as set forth in claim 1 wherein minority charge carriers are generated while the wafer is cooled from T 2 to T 3 .
8. A silicon wafer as set forth in claim 7 wherein minority charge carriers are generated by illuminating the wafer while the wafer is cooled from T 2 to T 3 .
9. A silicon wafer as set forth in claim 7 wherein minority charge carriers are generated by applying a current to the wafer while the wafer is cooled from T 2 to T 3 .
10. A silicon wafer as set forth in claim 1 wherein R 1 is at least about 250° C./sec.
11. A silicon wafer as set forth in claim 1 wherein R 1 is at least about 500° C./sec.
12. A silicon wafer as set forth in claim 1 wherein T 1 is at least about 500° C.
13. A silicon wafer as set forth in claim 1 wherein T 2 is less than about 500° C.
14. A silicon wafer as set forth in claim 1 wherein T 3 is less than about 150° C.
15. A silicon wafer as set forth in claim 1 wherein R 2 is less than about 10° C./sec.
16. A silicon wafer as set forth in claim 1 wherein the wafer comprises a second p-type dopant, the second p-type dopant being selected from the group consisting of Al, Ga and combinations thereof.
17. A silicon wafer as set forth in claim 1 wherein the silicon wafer is a slice of an ingot grow by the Czochralski process.
18. A silicon wafer as set forth in claim 1 wherein the silicon wafer forms part of a solar cell.
19. A silicon wafer as set forth in claim 1 wherein the silicon wafer is a stand-alone wafer.
20. A silicon wafer as set forth in claim 1 wherein T 1 is at least about 600° C., T 2 is less than about 250° C., R 1 is at least about 100° C./sec, T 3 is about 25° C. and R 2 is less than about 5° C./sec.