Semiconductor memory device capable of shortening erase time
View Patent ↗In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.
1. A semiconductor memory device comprising:
a memory cell array in which memory cells are provided;
word lines, including a first word line, a second word line and third word lines, connected to the memory cells, and the third word lines located between the first and second word lines; and
a control circuit,
wherein the memory cell array has at least two select transistors and memory cells connected in series between the select transistors, the select transistors have gates connected to at least two select lines, the first word line is connected to a first memory cell of the memory cells next to at least one of the select transistors, the second word line is connected to a second memory cell of the memory cells next to at least another one of the select transistors, and the third word line is connected to a third memory cell of the memory cells, and
wherein the control circuit erases the first, second and third memory cells in an erase operation, and the control circuit, in the erase operation, sets a first voltage to the first word line, sets a second voltage to the second word line, and sets a third voltage less than the first and second voltages to the third word lines.
2. The device according to claim 1 , further comprising
first transistors connected to the select lines;
a second transistor connected to the first word line;
a third transistor connected to the second word line; and
fourth transistors connected to the third word lines,
wherein gates of the first, second, third and fourth transistors are connected in common.
3. The device according to claim 2 ,
wherein in the erase operation, gates of the first, second, third and fourth transistors are set to a fourth voltage greater than a fifth voltage supplied to the select lines, and a sixth voltage greater than or equal to the fifth voltage is supplied to the first and second word lines.
4. The device according to claim 2 ,
wherein in the erase operation, gates of the first, second, third and fourth transistors are set to a seventh voltage greater than an eighth voltage supplied to the select lines minus a voltage Vth, wherein Vth is a threshold voltage of the first, second, third and fourth transistors, and the eighth voltage is supplied to the first and second word lines.
5. The device according to claim 2 ,
wherein the control circuit, in the erase operation, sets a ninth voltage greater than the first and second voltages to the select lines.
6. The device according to claim 1 ,
wherein the first and second memory cells are dummy cells.
7. The device according to claim 1 ,
wherein the control circuit verifies the third memory cells in an erase verify operation and does not verify the first and second memory cells in the erase verify operation.