Granted Patent B2

US 9,459,646 · App. 14/601,062 · Granted Oct 4, 2016

Abstract

Claims (77)

1. A voltage supply, comprising:

a voltage-divider network configured to divide a master voltage into at least one intermediate voltage;

a plurality of voltage zones, each voltage zone including at least one main circuit;

at least one soft rail configured to supply a voltage bias to the plurality of voltage zones, a voltage of the at least one soft rail being the at least one intermediate voltage; and

at least one buffer circuit configured to provide the voltage bias to the at least one soft rail and configured to maintain the voltage of the at least one soft rail at the at least one intermediate voltage.

2. The voltage supply according to claim 1 , wherein the at least one intermediate voltage scales with the master voltage.

3. The voltage supply according to claim 1 , wherein the voltage divider network includes high-impedance resistors electrically connected in series and the at least one intermediate voltage is a voltage at an interface between adjacent high-impedance resistors.

4. The voltage supply according to claim 1 , wherein the at least one buffer circuit includes a first voltage mirror having

a first field-effect transistor (FET) supplying the voltage bias to a first main circuit of the at least one main circuit, and

a second FET in series with a first current source and the second FET having a source electrically connected to the voltage divider network, wherein

a gate of the first FET electrically connects to a gate and drain of the second FET.

5. The voltage supply according to claim 1 , wherein the at least one buffer circuit corresponding to a respective voltage zone of the plurality of voltage zones uses circuit elements having a same over-voltage rating as circuit elements of the at least one main circuits corresponding to the same respective voltage zone of the plurality of voltage zones.

6. The voltage supply according to claim 1 , wherein

the plurality of voltage zones includes a first voltage zone, a second voltage zone, and a third voltage zone; and

the at least one soft rail includes a first soft rail corresponding to a first intermediate voltage βV dd and a second soft rail corresponding to a second intermediate voltage αV dd , wherein

the first voltage zone receives a voltage bias from a master-upper rail at the master voltage V dd and the first soft rail such that a voltage drop across the first voltage zone is (1−β)V dd ,

the second voltage zone receives the voltage bias from the first soft rail and the second rail, such that the voltage drop across the first voltage zone is (β−α)V dd , and

the third voltage zone receives a voltage bias from the second rail and a master-lower rail at a voltage V ss =0, such that the voltage drop across the first voltage zone is αV dd .

7. The voltage supply according to claim 1 , wherein

the at least one buffer circuit is configured to operate in a triode region conserving headroom when the master voltage is less than a predetermined threshold, and

the at least one buffer circuit is configured to operate in a saturation region when the master voltage exceeds the predetermined threshold.

8. The voltage supply according to claim 1 , wherein the at least one main circuit includes a high-swing main circuit, wherein

the high-swing main circuit receives a voltage bias from a first soft rail of the at least one soft rail, the first soft rail including a first buffer circuit, and the high-swing main circuit receives a voltage bias from a second soft rail of the at least one soft rail, the second soft rail including a second buffer circuit,

the first buffer circuit includes a voltage mirror having a first FET and a second FET, the second FET has a source electrically connected to the voltage divider network, a gate and drain of the second FET are electrically connected to a gate of the first FET, and a drain of the first FET is electrically connected to the main circuit,

the second buffer circuit includes a voltage mirror having a third FET and a fourth FET, the fourth FET has a source electrically connected to the voltage divider network, a gate and drain of the fourth FET are electrically connected to a gate of the third FET, and a drain of the third FET is electrically connected to the main circuit,

the first and the second FETs are both PMOS FETs and the third and the fourth FETs are both NMOS FETs, and

the first soft rail corresponds to a greater voltage than a voltage corresponding to the second soft rail.

9. The voltage supply according to claim 1 , wherein

the at least one main circuit includes a low input-impedance main circuit receiving a voltage bias from a master-upper rail and a first soft rail of the at least one soft rail, and the first soft rail includes a first buffer circuit, wherein

the first buffer circuit includes a voltage mirror having a first FET and a second FET, the second FET has a source electrically connected to the voltage divider network, a gate and drain of the second FET are electrically connected to a gate of the first FET, and a drain of the first FET is electrically connected to the main circuit,

the first and the second FETs are both NMOS FETs, and

the first soft rail corresponds to a voltage less than a voltage corresponding to the master-upper rail.

10. The voltage supply according to claim 1 , wherein

the at least one main circuit includes a high input-impedance main circuit receiving a voltage bias from a master-lower rail and a first soft rail of the at least one soft rail, and the first soft rail includes a first buffer circuit, wherein

the first buffer circuit includes a voltage mirror having a first FET and a second FET, the second FET has a source electrically connected to the voltage divider network, a gate and drain of the second FET are electrically connected to a gate of the first FET, and a drain of the first FET is electrically connected to the main circuit,

the first and the second FETs are both PMOS FETs, and

the first soft rail corresponds to a voltage greater than a voltage corresponding to the master-lower rail.

11. The voltage supply according to claim 4 , wherein the first current source is configured as half of a current mirror, the current mirror including a third FET and a fourth FET, the third FET being the first current source and the fourth FET being the other half of the current mirror, a current through the fourth FET being derived from a master current, and a gate of the third FET being electrically connected to a gate and a drain of the fourth FET.

12. The voltage supply according to claim 6 , wherein the

the first voltage zone corresponds to a first main circuit of the at least one main circuit having PMOS circuit elements;

the second voltage zone corresponds to a second main circuit of the at least one main circuit having cascode circuit elements; and

the third voltage zone corresponds to a third main circuit of the at least one main circuit having NMOS circuit elements.

13. The voltage supply according to claim 1 , wherein

the plurality of voltage zones includes a first voltage zone and a second voltage zone;

the at least one soft rail includes a first soft rail corresponding to a first intermediate voltage γV dd , wherein

the first voltage zone receives a voltage bias from a master-upper rail and the first soft rail such that a voltage drop across the first voltage zone is (1−γ)V dd , and

the second voltage zone receives a voltage bias from the first soft rail and a master-lower rail at a voltage V ss =0, such that a voltage drop across the second voltage zone is γV dd .

14. The voltage supply according to claim 6 , wherein

the plurality of voltage zones further includes a fourth voltage zone and a fifth voltage zone; and

the at least one soft rail further includes a third soft rail corresponding to a third intermediate voltage γV dd , wherein

the fourth voltage zone receives a voltage bias from the master-upper rail at the master voltage V dd and the third soft rail such that a voltage drop across the fourth voltage zone is (1−γ)V dd , and

the fifth voltage zone receives a voltage bias from the third soft rail and the master-lower rail, such that a voltage drop across the fifth voltage zone is γV dd .

15. The voltage supply according to claim 13 , wherein the

the first voltage zone corresponds to a first main circuit of the at least one main circuit having PMOS circuit elements; and

the second voltage zone corresponds to a second main circuit of the at least one main circuit having NMOS circuit elements.

16. The voltage supply according to claim 14 , wherein the

the fourth voltage zone corresponds to a fourth main circuit of the at least one main circuit having PMOS circuit elements; and

the fifth voltage zone corresponds to a fifth main circuit of the at least one main circuit having NMOS circuit elements.

17. A method of supplying voltage to a plurality of voltage zones, each voltage zone including at least one main circuit, the method comprising:

dividing a master voltage into at least one intermediate voltages using a voltage-divider network;

maintaining an at least one soft rail at the at least one intermediate voltages using an at least one buffer circuit electrically connected to the voltage-divider network; and

supplying a voltage bias to the at least one main circuit included in each of the plurality of voltage zones using the soft rail maintained at the least one intermediate voltages.

18. The method according to claim 17 , wherein the at least one buffer circuit includes a first voltage mirror having

a first field-effect transistor (FET) supplying the voltage bias to a first main circuit of the at least one main circuit, and

a second FET in series with a first current source and the second FET having a source electrically connected to the voltage divider network, wherein

a gate of the first FET electrically connects to a gate and drain of the second FET.

19. The method according to claim 17 , wherein

the plurality of voltage zones includes a first voltage zone, a second voltage zone, and a third voltage zone; and

the at least one soft rail includes a first soft rail corresponding to a first intermediate voltage βV dd and a second soft rail corresponding to a second intermediate voltage αV dd , wherein

the first voltage zone receives a voltage bias from a master-upper rail at the master voltage V dd and the first soft rail at the first intermediate voltage βV dd such that a voltage drop across the first voltage zone is (1−β)V dd ,

the second voltage zone receives a voltage bias from the first soft rail and the second rail, such that a voltage drop across the first voltage zone is (β−α)V dd , and

the third voltage zone receives a voltage bias from the second rail at the second intermediate voltage αV dd and a master-lower rail at a voltage V ss =0, such that a voltage drop across the first voltage zone is αV dd .

20. A voltage supply, comprising:

voltage-dividing means for dividing a master voltage into at least one intermediate voltage;

a plurality of voltage zones, each voltage zone including at least one main circuit;

voltage-bias-supplying means for supplying a voltage bias to the plurality of voltage zones, the voltage of the voltage-bias-supplying means being the at least one intermediate voltage; and

buffering means for providing the voltage bias to at least one soft rail while maintaining a voltage of the at least one soft rail at the at least one intermediate voltage.

Assignments (6)