Manufacturing method of non-volatile memory

1. A method for manufacturing a non-volatile memory, comprising:

providing a substrate comprising a first region and a second region;

performing a first patterning process to the first region to form a plurality of gate stack structures in the first region, and forming a first sidewall oxide layer to cover sidewalls and an upper surface of each of the plurality of gate stack structures after forming the plurality of gate stack structures;

forming a first high-temperature deposition layer on the first sidewall oxide layer after the first sidewall oxide layer is formed;

forming a protective layer on the first high-temperature deposition layer after the first high-temperature deposition layer is formed;

performing an ion implantation process to the second region after forming the protective layer;

forming a gate material layer in the second region after performing the ion implantation process to the second region;

removing the protective layer in the first region to expose the underlying first high-temperature deposition layer after the gate material layer is formed in the second region;

etching the first high-temperature deposition layer to form first spacers on the sidewalls of the plurality of gate stack structures covered with the first sidewall oxide layer and to expose a part of the first sidewall oxide layer on the upper surfaces of the plurality of gate stack structures;

performing a second patterning process to the second region to form the plurality of gate structures in the second region after the first spacers are formed; and

forming a second sidewall oxide layer to cover sidewalls of each of the plurality of gate structures.

2. The method of claim 1 , wherein the first region is a memory cell region, and the second region is a peripheral circuit region.

3. The method of claim 1 , wherein each of the plurality of gate stack structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer and at least a control gate.

4. The method of claim 1 , wherein each of the plurality of gate structures comprises a patterned gate oxide layer and a gate.

5. The method of claim 1 , further comprising forming a second high-temperature deposition layer on the gate material layer after the gate material layer is formed in the second region.

6. The method of claim 5 , further comprising removing the second high-temperature deposition layer, before removing the protective layer in the first region.

7. The method of claim 1 , further comprising forming a second spacer outside of the first spacer and forming a dielectric layer outside of the second sidewall oxide layer after the second sidewall oxide layer is formed.

8. The method of claim 1 , wherein a material of the protective layer is silicon nitride or polysilicon.

9. The method of claim 1 , wherein the protective layer is a two-layered structure, and the two-layered structure comprises an inner layer and an outer layer.

10. The method of claim 9 , wherein a material of the inner layer is silicon nitride, and a material of the outer layer is silicon oxynitride.

11. The method of claim 1 , wherein the first sidewall oxide layer is formed at a temperature higher than a temperature at which the second sidewall oxide layer is formed.

12. The method of claim 11 , wherein forming the first sidewall oxide layer comprises an in-situ steam generation process or a wet oxidation process.

13. The method of claim 11 , wherein forming the second sidewall oxide layer comprises a rapid thermal oxidation process.