Semiconductor memory device with ONO stack
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first gate layer and a first dielectric layer thereon, and a shallow trench isolation (STI) in the substrate and surrounding the first gate layer and the first dielectric layer; removing the first dielectric layer; forming a first spacer on the sidewall of the STI above the first gate layer; and using the first spacer as mask to remove part of the first gate layer and part of the substrate for forming a first opening while defining a first gate structure and a second gate structure.
1. A semiconductor device, comprising:
a substrate;
a first gate structure and a second gate structure on the substrate, wherein the first gate structure has a first inclined surface and the second gate structure has a second inclined surface facing the first inclined surface;
a spacer in part of the substrate and between the first gate structure and the second gate structure;
a shallow trench isolation (STI) surrounding the first gate structure and the second gate structure, wherein the STI is in direct contact with the first gate structure and the second gate structure, wherein a bottom of the spacer is even with a bottom of the STI; and
an oxide-nitride-oxide (ONO) stack on the STI, the spacer, the first gate structure, and the second gate structure.
2. The semiconductor device of claim 1 , further comprising a third gate structure between the first gate structure and the substrate and a fourth gate structure between the second gate structure and the substrate.
3. The semiconductor device of claim 2 , wherein the third gate structure and the fourth gate structure comprise undoped polysilicon.
4. The semiconductor device of claim 1 , wherein the first gate structure and the second gate structure comprise doped polysilicon.
5. A semiconductor device, comprising:
a substrate;
a first gate structure and a second gate structure on the substrate, wherein the first gate structure has a first inclined surface and the second gate structure has a second inclined surface facing the first inclined surface, wherein the first gate structure and the second gate structure comprise doped polysilicon;
a shallow trench isolation (STI) surrounding the first gate structure and the second gate structure;
a dielectric layer between the first gate structure and the second gate structure and in part of the substrate, wherein a top surface of the dielectric layer is lower than a top surface of the STI, wherein the STI is in direct contact with the first gate structure and the second gate structure; and
an oxide-nitride-oxide (ONO) stack on the STI, the dielectric layer, the first gate structure, and the second gate structure.
6. The semiconductor device of claim 5 , further comprising a third gate structure between the first gate structure and the substrate and a fourth gate structure between the second gate structure and the substrate.
7. The semiconductor device of claim 6 , wherein the third gate structure and the fourth gate structure comprise undoped polysilicon.