Systems and methods for transforming a central processing unit (CPU) socket into a memory and/or input/output (I/O) expander
View Patent ↗Systems and methods for transforming a Central Processing Unit (CPU) socket into a memory and/or Input/Output (I/O) expander. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of CPU sockets, each of the CPU sockets having one or more cores, and each of the one or more cores being associated with a respective one or more electronic circuits, the one or more electronic circuits including at least one of: a memory controller or an input/output (I/O) controller; and a Basic Input/Output System (BIOS) circuit coupled to the plurality of CPU sockets, the BIOS circuit having access to program instructions that, upon execution by the BIOS, cause the IHS to: initialize the plurality of CPU sockets; and report an electronic circuit associated to a first core of a first CPU socket as being instead associated with a second core of a second CPU socket.
1. An Information Handling System (IHS), comprising:
a plurality of Central Processing Unit (CPU) circuits, wherein each of the CPU circuits comprises a core and at least one of: a memory controller or an input/output (I/O) lane; and
a Basic Input/Output System (BIOS) coupled to the plurality of CPU circuits, the BIOS having program instructions stored thereon that, upon execution by the IHS, cause the IHS to:
identify a memory controller or I/O lane of a first CPU circuit as belonging to a second CPU circuit;
identify the first CPU circuit as not having any cores; and
create or modify an Advanced Configuration and Power Interface (ACPI) System Locality Information Table (SLIT) to identify a memory controller of the first CPU circuit as being a remote memory coupled to the second CPU circuit.
2. The IHS of claim 1 , wherein the plurality of CPU circuits include a single multi-core processor.
3. The IHS of claim 1 , wherein each core in each of the plurality of CPU circuits is configured to operate as a logical processor.
4. The IHS of claim 1 , wherein the memory controller or I/O lane is physically disposed closer to a first core of the first CPU circuit than to a second core of the second CPU circuit.
5. The IHS of claim 1 , wherein the identifying enables a memory controller of the second CPU circuit to communicate with two or more dual in-line memory modules (DIMMs).
6. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to create or modify a Local Advanced Programmable Interrupt Controller (LAPIC) table of an Advanced Configuration and Power Interface (ACPI).
7. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to modify an Advanced Configuration and Power Interface (ACPI) Static Resource Affinity Table (SRAT) to identify a memory controller of the first CPU circuit as being coupled directly to a core of the second CPU circuit.
8. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to create or modify Advanced Configuration and Power Interface (ACPI) proximity (PXM) information to report one or more Peripheral Component Interconnect Express (PCIe) root ports of the first CPU circuit as logical PCIe root ports belonging to the second CPU circuit.
9. The IHS of claim 1 , wherein the program instructions, upon execution by the IHS, further cause the IHS to, in response to a System Management Mode (SMM) of operation being invoked to address a memory or I/O error of the first CPU circuit during Operating System (OS) runtime, report the error as having been originated by the second CPU circuit.
10. The IHS of claim 1 , wherein the identifying operations occur before the IHS boots into an Operating System (OS).
11. A computer-implemented method, comprising:
initializing a plurality of Central Processing Unit (CPU) circuits within a multi-core processor of an Information Handling System (IHS), wherein each of the CPU circuits comprises at least a core and an electronic circuit associated with the core, and wherein each electronic circuit includes at least one of: a memory controller or an input/output (I/O) lane;
prior to the IHS booting an Operating System (OS), reporting an electronic circuit of a first core of a first CPU circuit as belonging to a second core of a second CPU circuit, wherein the electronic circuit includes an I/O extender local to the first core of the first CPU circuit; and
modifying Advanced Configuration and Power Interface (ACPI) proximity (PXM) information to report one or more Peripheral Component Interconnect Express (PCIe) root ports local to the first core of the first CPU circuit as logical PCIe root ports local to the second core of the second CPU circuit.
12. The computer-implemented method of claim 11 , wherein the electronic circuit includes a memory controller local to the first core of the first CPU circuit.
13. The computer-implemented method of claim 12 , further comprising creating or modifying a Local Advanced Programmable Interrupt Controller (LAPIC) table of an Advanced Configuration and Power Interface (ACPI), wherein the LAPIC table is configured to identify the second core of the second CPU circuit, and wherein the LAPIC table is configured not to identify the first core of the first CPU circuit.
14. The computer-implemented method of claim 13 , further comprising creating or modifying an Advanced Configuration and Power Interface (ACPI) Static Resource Affinity Table (SRAT) to identify the memory controller as being coupled directly to the second core of the second CPU circuit.
15. The computer-implemented method of claim 14 , further comprising creating or modifying an Advanced Configuration and Power Interface (ACPI) System Locality Information Table (SLIT) to identify the memory controller as including a remote memory coupled to the second core of the second CPU circuit.
16. The computer-implemented method of claim 11 , further
comprising, in response to a System Management Mode (SMM) of operation being invoked to address a memory or I/O error of the first core of the first CPU circuit during Operating System (OS) runtime, reporting the error as having been originated by the second core of the second CPU circuit.
17. A hardware memory device having program instructions stored thereon that, upon execution by an Information Handling System (IHS), cause the IHS to:
initialize a plurality of Central Processing Unit (CPU) circuits, wherein each of the CPU circuits comprises at least a core and a memory controller;
create or modify a Local Advanced Programmable Interrupt Controller (LAPIC) table of an Advanced Configuration and Power Interface (ACPI), wherein the LAPIC table is configured to identify a second core of a second CPU circuit, and wherein the LAPIC table is configured not to identify a first core of a first CPU circuit;
create or modify an ACPI Static Resource Affinity Table (SRAT) to identify a memory controller corresponding to the first core of the first CPU circuit as belonging to the second core of the second CPU circuit;
create or modify an ACPI System Locality Information Table (SLIT) to identify the memory controller as including a remote memory coupled to the second core of the second CPU circuit; and
in response to a System Management Mode (SMM) of operation being invoked to address a memory or I/O error of the first core of the first CPU circuit during Operating System (OS) runtime, identifying the error as having been originated by the second core of the second CPU circuit.