Digital baud rate clock recovery of heavily ISI-induced signals
System and method for digitally equalizing a data channel having wide channel impulse response for clock recovery of heavily ISI-induced received signals operating at one sample per symbol, according to which the received signal is pre-processed to provide a received signal with modified constellation, which is pre-processed for the decision process of signal with Inter-Symbol Interference by introducing controlled ISI to the received signal. The decision process is performed, based on a higher order vocabulary according to the introduced controlled ISI.
1. A system for digitally equalizing a data channel having wide channel impulse response for clock recovery of heavily Inter-Symbol Interference induced (ISI-induced) signals, comprising:
a) a one sample per symbol analog-to-digital converter (ADC), for sampling the received signal and converting it to a digital form;
b) a delay element for delaying said received signal by a predetermined time delay, required for sampling said received signal at appropriate timing;
c) a modified Muller & Mueller Timing Error Detector (TED) for detecting the timing error of said received signal, said Timing Error Detector having two inputs, one input for receiving a delayed sequence of the received signal samples and another input for receiving a filtered version of the data symbols being modified data symbols, with controlled ISI and modified constellation;
d) a Feed-Forward Equalizer having a predetermined number of taps, for receiving said signal samples and introducing correction factors to the ISI added to the samples of said received signal by said data channel, to thereby generate the modified data symbols;
e) a decision circuit, fed by said Feed-Forward Equalizer (FFE), for extracting the modified data symbols from the received signal and for generating an error signal used to adjust the taps of said FFE; and
f) an adaptive filter for producing the least mean squares of said error signal and inputting said least mean squares into said FFE for adjusting and optimizing its tap coefficients, according to the channel dynamics.
2. A system according to claim 1 , in which the Feed-Forward Equalizer is implemented by a Finite Impulse Response (FIR) filter.
3. A system according to claim 1 , in which the timing error signal at the output of the TED is produced using a modified Mueller and Muller algorithm for a wide channel impulse response.
4. A system according to claim 1 , being adapted to perform clock recovery for high order modulations, including:
PAM-2;
PAM-4;
PAM-8;
PAM-16;
Quadrature Phase Shift Keying (QPSK);
QAM-8;
QAM-16.
5. A system according to claim 1 , being adapted to perform clock recovery for dada networks, including:
data center intra-connection
data center interconnection;
metropolitan point-to-point connections;
metropolitan Wavelength-Division Multiplexing (WDM).
6. A system according to claim 1 ; in which the FIT taps are adapted using a Least Mean Square (LMS) filter, producing the least mean squares of the error signal.
7. A system according to claim 1 , in which the data channel is converted into a modified channel having an impulse response of [1/2 1/2].