Resistive random access memory structure

1. A semiconductor structure, comprising:

a bottom electrode having a first width;

a dielectric structure having a second width formed over the bottom electrode;

a top electrode having a third width formed over the dielectric structure; and

a hard mask structure formed over the top electrode,

wherein the second width of the dielectric structure is greater than the first width of the bottom electrode and the first width of the bottom electrode is greater than the third width of the top electrode.

2. The semiconductor structure as claimed in claim 1 , wherein a distance between an edge of the dielectric structure and an edge of the bottom electrode is in a range from about 1 nm to about 5 nm.

3. The semiconductor structure as claimed in claim 1 , further comprising:

a via structure formed through the hard mask structure; and

a bit line structure formed over the via structure,

wherein the bit line is electrically connected to the top electrode through the via structure.

4. A semiconductor structure, comprising:

a resistive random access memory structure formed over a substrate, wherein the resistive random access memory structure comprises

a bottom electrode formed over the substrate;

a dielectric structure formed over the bottom electrode;

a top electrode formed over the dielectric structure; and

a hard mask structure formed over the top electrode;

an etch stop layer formed over a top surface of the hard mask structure and over sidewalls of the hard mask structure, the top electrode, the dielectric structure, and the bottom electrode; and

an inter-metal dielectric layer formed around the resistive random access memory structure,

wherein the dielectric structure comprises an extending portion extending into the inter-metal dielectric layer, and neither the bottom electrode nor the top electrode covers the extending portion, and a bottom surface of the extending portion of the dielectric structure is substantially level with a top surface of the bottom electrode.

5. The semiconductor structure as claimed in claim 4 , wherein the extending portion of the dielectric structure has a width in a range from about 1 nm to about 5 nm.

6. The semiconductor structure as claimed in claim 4 , wherein the etch stop layer further covers a top surface, a sidewall, and a bottom surface of the extending portion of the dielectric structure.

7. The semiconductor structure as claimed in claim 4 , further comprising:

a via structure formed through the etch stop layer and the hard mask structure; and

a bit line structure formed over the via structure,

wherein the bit line is electrically connected to the resistive random access memory structure through the via structure.

8. The semiconductor structure as claimed in claim 4 , wherein the substrate comprises a memory cell transistor, and the memory cell transistor is electrically connected to the resistive random access memory structure.

9. A resistive random access memory structure, comprising:

a bottom electrode formed over a substrate;

a dielectric structure formed over the bottom electrode;

a top electrode formed over the dielectric structure;

a hard mask structure formed over the top electrode;

a via structure formed through the hard mask structure; and

a bit line structure formed over the via structure,

wherein the hard mask structure and the dielectric structure are both wider than the top electrode, and the top electrode is wider than the bottom electrode.

10. The resistive random access memory structure as claimed in claim 9 , further comprising:

an inter-metal dielectric layer formed around the bottom electrode, the dielectric structure, the top electrode, and the hard mask structure,

wherein the dielectric structure comprises an extending portion extending into the inter-metal dielectric layer.

11. The resistive random access memory structure as claimed in claim 1 , wherein the second width of the dielectric structure is substantially equal to a width of the hard mask structure.

12. The semiconductor structure as claimed in claim 1 , further comprising:

a via structure formed through the hard mask structure.

13. The semiconductor structure as claimed in claim 4 , wherein a width of the dielectric structure is substantially equal to a width of the hard mask structure.

14. The semiconductor structure as claimed in claim 4 , wherein a bottom surface of the dielectric structure is substantially flat.

15. The semiconductor structure as claimed in claim 1 , further comprising:

an etch stop layer covering sidewalls of the hard mask structure, a top surface of the hard mask structure, a bottom surface of the hard mask structure, sidewalls of the top electrode, sidewalls of the dielectric structure, a top surface of the dielectric structure, a bottom surface of the dielectric structure, and sidewalls of the bottom electrode.

16. The semiconductor structure as claimed in claim 4 , wherein the dielectric structure is made of zirconium dioxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HMO), hafnium zirconium oxide (HfZrO), zirconium silicate, zirconium aluminate, silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or hafnium dioxide-alumina (HfO 2 —Al 2 O 3 ) alloy.

17. The semiconductor structure as claimed in claim 4 , wherein a sidewall of the dielectric structure is substantially aligned with a sidewall of the hard mask structure.

18. The semiconductor structure as claimed in claim 9 , wherein a difference between a width of the top electrode and a width of the bottom electrode is in a range from about 1 nm to about 4 nm.

19. The semiconductor structure as claimed in claim 18 , wherein a distance between an edge of the top electrode and an edge of the dielectric structure is in a range from about 1 nm to about 5 nm.

20. The semiconductor structure as claimed in claim 9 , further comprising:

an etch stop layer formed over top surfaces and bottom surfaces of the hard mask structure and the dielectric structure and over sidewalls of the hard mask structure, the top electrode, the dielectric structure, and the bottom electrode.