Extended-drain transistor using inner spacer

1. An MOS device with increased drain-source voltage (Vds), the MOS device comprising:

a source region and a drain region deposited on a substrate; and

a gate region comprising an inner spacer configured to extend the drain region,

wherein:

the inner spacer is formed attached to an isolation spacer that isolates the drain region from the gate region, and

the inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

2. The MOS device of claim 1 , wherein the inner spacer comprises at least one of silicon nitride, silicon carbide, or an oxide inner spacer, wherein the oxide inner spacer comprises silicon oxide.

3. The MOS device of claim 1 , wherein a width of the inner spacer depends on an employed technology node, wherein the width of the inner spacer comprises approximately 20 percent of an MOS channel length.

4. The MOS device of claim 1 , wherein a length of a drain extension achieved by forming the inner spacer is based on a width of the inner spacer.

5. The MOS device of claim 1 , wherein the inner spacer is configured to increase the Vds of the MOS device by extending the drain region, wherein the inner spacer is configured to extend the drain region to reduce the electric field in the portion of the conductive band of the MOS device.

6. The MOS device of claim 1 , wherein the inner spacer is configured to reduce hot carrier injection (HCl) and gate-induced drain leakage (GIDL).

7. The MOS device of claim 1 , wherein addition of the inner spacer in the gate region does not affect an MOS device density and is compatible with design rules.

8. The MOS device of claim 1 , wherein for partial-gate-last processes the inner spacer is formed over a protection layer covering a dielectric layer formed on the substrate in the gate region, wherein the partial-gate-last processes include a 28 nanometer (nm) technology node.

9. The MOS device of claim 1 , wherein for full-gate-last processes the inner spacer is formed over the substrate in the gate region, wherein the full-gate-last processes include 20 nm and smaller technology nodes.

10. A method for providing an MOS device with increased drain-source voltage (Vds), the method comprising:

forming a source region and a drain region on a substrate;

forming a gate region isolated from the drain region by an isolation spacer; and

forming an inner spacer in the gate region attached to the isolation spacer,

wherein:

the inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

11. The method of claim 10 , wherein forming the inner spacer comprises forming an oxide inner spacer, wherein forming the oxide inner spacer comprises using silicon oxide, and wherein forming the inner spacer comprises using one of silicon nitride or silicon carbide.

12. The method of claim 10 , further comprising determining a width of the inner spacer based on an employed technology node, wherein the width of the inner spacer comprises approximately 20 percent of an MOS channel length.

13. The method of claim 10 , wherein forming the inner spacer results in an extension of a drain length, and wherein a drain-length extension is based on a width of the inner spacer.

14. The method of claim 10 , further comprising:

configuring the inner spacer to increase the Vds of the MOS device by extending the drain region; and

configuring the inner spacer to reduce the electric field in the portion of the conductive band of the MOS device by extending the drain region.

15. The method of claim 10 , further comprising configuring the inner spacer to reduce hot carrier injection (HCl) and gate-induced drain leakage (GIDL).

16. The method of claim 10 , wherein forming the inner spacer in the gate region does not affect an MOS device density and is compatible with design rules.

17. The method of claim 10 , further comprising, for partial-gate-last processes, forming the inner spacer over a protection layer covering a dielectric layer formed on the substrate in the gate region, wherein the partial-gate-last processes include a 28 nanometer (nm) technology node.

18. The method of claim 10 , further comprising, for full-gate-last processes, forming the inner spacer over the substrate in the gate region, wherein the full-gate-last processes include 20 nm and smaller technology nodes.

19. A communication device, comprising:

a radio-frequency (RF) circuitry configured to communicate RF signals;

one or more processors; and

memory coupled to the one or more processors,

wherein at least one of the RF circuitry, one or more processors, or the memory comprises an MOS device with increased drain-source voltage (Vds), the MOS device comprising:

a source region and a drain region deposited on a substrate;

a gate region isolated from the drain region by an isolation spacer; and

an inner spacer formed in the gate region and attached to the isolation spacer,

wherein:

the inner spacer is configured to extend the drain region to modify an electric field in a portion of a conductive band of the MOS device.

20. The communication device of claim 19 , wherein:

the inner spacer comprises at least one of silicon nitride, silicon carbide, or an oxide inner spacer,

the oxide inner spacer comprises silicon oxide,

a width of the inner spacer depends on an employed technology node,

the width of the inner spacer comprises approximately 20 percent of an MOS channel length,

a length of a drain extension achieved by forming the inner spacer is based on a width of the inner spacer,

the inner spacer is configured to increase the Vds of the MOS device by extending the drain region, and

the inner spacer is configured to reduce hot carrier injection (HCl) and gate-induced drain leakage (GIDL).