IP Library Granted Patent US 9,443,914
Granted Patent B2
US 9,443,914 · App. 14/612,979 · Granted Sep 13, 2016

Array substrate and manufacturing method thereof

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Quick Facts
Patent No.
US 9,443,914
App. No.
14/612,979
Granted
Sep 13, 2016
Kind
B2
Abstract

An array substrate for an FPD device, wherein, in each of the display pixel dots in the display area, the first connection wiring is connected to the pixel electrode via a contact hole while the second connection wiring is connected to the signal line via a contact hole; in each of the dummy pixel dots, the first connection wiring is not electrically connected to any of the pixel electrodes; in the peripheral non-viewing area extending in a direction along the signal line, the first connection wiring extends in a direction away from the scanning line at a position distanced from the switching element, and has a pad having a width larger than other part of the first connection wiring at its distal end.

Claims (10)

1. An array substrate comprising:

an array of scanning lines and an array of signal lines that intersect the scanning lines;

a switching element and a pixel electrode, which are arranged for each intersection of the scanning and signal lines;

a view area, in which display pixel dots are arrayed and which corresponds to an image display area of a flat-panel display (FPD) device; and

a dummy pixel area, in which dummy pixel dots are arrayed and which is in a peripheral non-viewing area that surrounds the view area; wherein,

in each of the display pixel dots and in each of the dummy pixel dots, a first connection wiring and a second connection wiring are arranged to extend respectively from one terminal and another terminal of the switching element;

in each of the display pixel dots in the display area, the first connection wiring is connected to the pixel electrode via a contact hole while the second connection wiring is connected to the signal line via a contact hole; in each of the dummy pixel dots, the first connection wiring is not electrically connected to any of the pixel electrodes;

in the peripheral non-viewing area extending in a direction along the signal line, the first connection wiring extends in a direction away from the scanning line at a position distanced from the switching element, and has a pad having a width larger than other part of the first connection wiring at its distal end;

wherein, in each of the display and dummy pixel dots, a continuous pattern, which is formed of a polysilicon film or other film capable to form wirings and a semiconductor film, is arranged and comprises the first and second connecting wiring patterns and the semiconductor film of the switching element; and

wherein the second connection wiring in each of the dummy pixel dots is not electrically connected with the signal line, and has an oblique shift portion that runs obliquely from the signal line direction toward the interior of the pixel dot, so as to shift position in the scanning line direction, of a line segment of the second connection wiring, which substantially runs along the signal line.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2015
From: AMANO, YUICHI
To: JAPAN DISPLAY INC.
Reel/Frame 035404/0223 →