Apparatus and methods for fast charge pump holdover on signal interruption
Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLL's loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range.
1. An apparatus comprising:
a detector circuit configured to determine whether or not an atypical amount of phase error exists in a phase-locked loop (PLL) or a delay-locked loop (DLL); and
a holdover circuit configured to enter a holdover state in which a frequency/delay control signal is maintained steady, wherein the holdover state is initiated asynchronously when the detector circuit has determined that the atypical amount of phase error exists.
2. The apparatus of claim 1 , further comprising a controller configured to selectively enable and/or bypass the detector and maintain the holdover state based on a known state of the system.
3. The apparatus of claim 2 , further comprising a multiplexer, wherein a plurality of reference clock signals are provided as inputs to the multiplexer, wherein the output of the multiplexer is provided as a reference clock signal for the PLL or DLL, wherein the controller is configured to select a different input of the multiplexer for the output of the multiplexer and to exit from the holdover state.
4. The apparatus of claim 1 , further comprising a switch disposed in a signal path between charge pumps and the VCO of the PLL or delay lines of the DLL, wherein the holdover circuit is configured to control the switch such that the switch is open circuit in the holdover state.
5. The apparatus of claim 1 , wherein the detector circuit further comprises:
an OR gate having a first input, a second input, and an output, wherein the first input is coupled to a first output of a phase frequency detector, wherein the second input is coupled to a second output of the phase frequency detector;
a delay circuit having an input and an output, wherein the input of the delay circuit is operatively coupled to the output of the OR gate; and
an AND gate having a first input, a second input, and an output, wherein the first input is operatively coupled to the output of the OR gate, wherein the second input is operatively coupled to the output of the delay circuit, wherein the output of the AND gate is configured to initiate the holdover state.
6. The apparatus of claim 5 , wherein a delay of the delay circuit is greater than a minimum reset pulse width of the phase frequency detector.
7. The apparatus of claim 5 , wherein the delay of the delay circuit is configurable.
8. The apparatus of claim 1 , wherein the phase detector comprises an XOR gate having inputs configured to receive reference clock signals and an output, further comprising a switch disposed in a signal path between the XOR gate and the VCO of the PLL or delay lines of the DLL, wherein the holdover circuit is configured to control the switch such that the switch is open circuit in the holdover state.
9. The apparatus of claim 1 , wherein the detector circuit further comprises:
an exclusive-OR (XOR) gate having a first input, a second input, and an output, wherein the first input is coupled to a first output of a phase frequency detector, wherein the second input is coupled to a second output of the phase frequency detector;
a delay circuit having an input and an output, wherein the input of the delay circuit is operatively coupled to the output of the XOR gate; and
an AND gate having a first input, a second input, and an output, wherein the first input is operatively coupled to the output of the XOR gate, wherein the second input is operatively coupled to the output of the delay circuit, wherein the output of the AND gate is configured to initiate the holdover state.
10. A method of initiating a holdover state comprising:
determining whether or not an atypical amount of phase error exists in a phase-locked loop or a delay-locked loop; and
entering a holdover state in which a frequency/delay control signal is maintained steady, wherein the holdover state is asynchronously initiated when the existence of the atypical amount of phase error has been detected.
11. The method of claim 10 , further comprising maintaining the holdover state based on a known state of the system.
12. The method of claim 11 , further comprising providing a plurality of reference clock signals as inputs to a multiplexer, wherein the output of the multiplexer is provided as a reference clock signal for the PLL or DLL, further comprising selecting a different input of the multiplexer for the output of the multiplexer and exiting from the holdover state.
13. The method of claim 10 , further comprising controlling a switch disposed in a signal path between charge pumps and the VCO of the PLL or delay lines of the DLL, wherein the switch is controlled such that the switch is open circuit in the holdover state.
14. The method of claim 10 , further comprising:
ORing a first output of a phase frequency detector with a second output of the phase frequency detector to generate a trigger pulse signal;
delaying the trigger pulse signal to generate a delayed pulse signal; and
initiating the holdover state based on an ANDing of the trigger pulse signal and the delayed pulse signal.
15. The method of claim 14 , wherein the delayed pulse signal is delayed from the trigger pulse signal by an amount greater than a minimum reset pulse width of a phase frequency detector.
16. The method of claim 14 , further comprising adjusting the amount of delay between the delayed pulse signal and the trigger pulse signal.
17. The method of claim 10 , wherein determining whether or not the atypical amount of phase error exists further comprising exclusive ORing reference clock signals with an XOR gate, further open circuiting a switch disposed in a signal path between the XOR gate and the VCO of the PLL or delay lines of the DLL in the holdover state.
18. The method of claim 10 , further comprising:
exclusive ORing a first output of a phase frequency detector with a second output of the phase frequency detector to generate a trigger pulse signal;
delaying the trigger pulse signal to generate a delayed pulse signal; and
initiating the holdover state based on an ANDing of the trigger pulse signal and the delayed pulse signal.
19. An apparatus comprising:
a means for determining whether or not an atypical amount of phase error exists in a phase-locked loop or a delay-locked loop; and
a means for entering a holdover state in which a frequency/delay control signal is maintained steady, wherein the holdover state is asynchronously initiated when the existence of the atypical amount of phase error has been detected.
20. The apparatus of claim 1 , wherein the detector circuit further comprises:
an OR or XOR gate having a first input, a second input, and an output, wherein the first input is coupled to a first output of a phase frequency detector, wherein the second input is coupled to a second output of the phase frequency detector; and
a logic time detection circuit configured to compare a timing characteristic of the output relative to a threshold time delay and generate a logic comparator output signal configured to initiate the holdover state, wherein the threshold time delay is configurable.
21. The method of claim 10 further comprising:
ORing or XORing a first output of a phase frequency detector with a second output of the phase frequency detector to generate a trigger pulse signal; and
comparing a timing characteristic of the trigger pulse signal to a threshold time delay to generate a logic comparator output signal configured to initiate the holdover state, wherein the threshold time delay is configurable.