Semiconductor device and method of forming the same
A semiconductor device includes a plurality of gate structures, a source/drain region, a first dielectric layer, and a floating spacer. The gate structures are disposed on a substrate, and each gate structure includes a gate electrode, a capping layer and a spacer surrounding the gate electrode and the capping layer. The source/drain region is disposed at two sides of the gate electrode. The first dielectric layer is disposed on the substrate and has a height being less than a height of the gate electrode. The floating spacer is disposed on a side wall of the spacer, and also on the first dielectric layer.
1. A semiconductor device, comprising:
a plurality of gate structures disposed on a substrate, wherein each of the gate structures comprises:
a gate electrode
a capping layer, disposed on the gate electrode; and
a spacer surrounding the gate electrode and the capping layer;
a source/drain region disposed at two sides of each gate electrode;
a contact etching stop layer (CESL) disposed on the substrate;
a first dielectric layer disposed on the CESL; and
a floating spacer disposed on a sidewall of each spacer and the first dielectric layer.
2. The semiconductor device according to claim 1 , wherein the floating spacer covers a top portion of the spacer.
3. The semiconductor device according to claim 1 , wherein a portion of the floating spacer covers the gate electrode.
4. The semiconductor device according to claim 1 , wherein a top portion of the spacer is partially exposed by the floating spacer.
5. The semiconductor device according to claim 1 , wherein the capping layer comprises a multilayer structure.
6. The semiconductor device according to claim 1 , wherein the first dielectric layer having a height less than a height of the gate electrode.
7. The semiconductor device according to claim 6 , further comprising:
a second dielectric layer disposed on the first dielectric layer; and
a contact plug disposed in the second dielectric layer and the first dielectric layer, wherein the contact plug is electrically connected to the source/drain region.
8. The semiconductor device according to claim 7 , wherein the contact plug directly contacts the floating spacer.
9. The semiconductor device according to claim 7 , wherein a portion of the first dielectric layer is disposed between the contact plug and the gate structures.
10. The semiconductor device according to claim 1 , wherein the floating spacer contacts a top portion of a sidewall of the CESL.
11. The semiconductor device according to claim 1 , further comprising:
a second dielectric layer disposed on the first dielectric layer and level with the gate structure;
a third dielectric layer disposed on the second dielectric layer; and
a contact plug, disposed in the third dielectric layer, the second dielectric layer and the first dielectric layer, wherein the contact plug is electrically connected to the source/drain region.