Graphics processing architecture employing a unified shader
View Patent ↗A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
1. A graphics processor, comprising:
a unified shader; and
an arbiter circuit operative to carry out an arbitration scheme to determine which of a plurality of inputs to provide to the unified shader;
wherein the unified shader is operatively coupled to the arbiter circuit and comprises:
a processor unit configured to simultaneously perform vertex manipulation operations and pixel manipulation operations based on the provided inputs to the unified shader.
2. The graphics processor of claim 1 wherein the unified shader further comprises:
a data store, operatively coupled to the processor unit, configured to simultaneously store pixel data and vertex data.
3. The graphics processor of claim 2 wherein the unified shader further comprises:
an instruction store, operatively coupled to the processor unit and operative to store both vertex manipulation instructions and pixel manipulation instructions.
4. The graphics processor of claim 1 wherein the processor unit comprises at least two logically partitioned sections wherein at least one of the partitions performs vertex manipulation operations simultaneously with another of the logically partitioned sections that performs pixel operations.
5. The graphics processor of claim 4 wherein one of the at least two logically partitioned sections of the processor unit of the unified shader comprises a floating point arithmetic operation section and wherein another of the at least two logically partitioned sections of the processor unit of the unified shader comprises a scaler operation section.
6. The graphics processor of claim 5 wherein the plurality of inputs include a vertex data input and a pixel data input and wherein the arbitration scheme is configured to generate a control signal for determining which one of the vertex data input and the pixel data input is to be transmitted to the unified shader.
7. The graphics processor of claim 1 wherein the unified shader is operative to simultaneously perform vertex manipulation operations and pixel manipulation operations that are at various degrees of completion.
8. The graphics processor of claim 1 wherein the plurality of inputs include a vertex data input and a pixel data input and wherein the arbitration scheme employed by the arbiter circuit selects the vertex data input if there are enough resources available in the unified shader to operate on the vertex data.