IP Library › Granted Patent US 9,299,308
Granted Patent B2
US 9,299,308 · App. 14/615,410 · Granted Mar 29, 2016

Display device

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Quick Facts
Patent No.
US 9,299,308
App. No.
14/615,410
Granted
Mar 29, 2016
Kind
B2
Abstract

A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

Claims (52)

1. A shift register circuit comprising:

a plurality of cascaded stages including a first start-stage and M stages (M is natural number equal to or greater than 2);

a start signal line electrically connected with the first start-stage;

a plurality of output signal lines electrically connected with M stages respectively for applying a conducting potential which makes a pixel transistor electrically connecting with the output signal line conductive;

a first clock signal line electrically connected with the plurality of cascaded stages and applying a first clock signal;

a second clock signal line electrically connected with the plurality of cascaded stages and applying a second clock signal,

a third clock signal line electrically connected with the plurality of cascaded stages and applying a third clock signal,

wherein the first clock, the second clock and the third clock become the conducting potential in order,

wherein M stages and the first start-stage include an output transistor, a first node and a first node setting transistor,

wherein the output transistor of M stages has a first electrode which is electrically connected with the output signal line, a second electrode which is electrically connected with the first clock signal line or the third clock signal line, and a gate electrode which is electrically connected with the first node,

wherein the first node setting transistor of M stages has a first electrode which is electrically connected with the first node, a second electrode and gate electrode which are electrically connected with the first electrode of the output transistor of a previous stage,

wherein the output transistor of the first start-stage has a first electrode which is electrically connected with the second electrode of the first node setting transistor of a first stage of M stages, a second electrode which is electrically connected with the third clock signal line, a gate electrode which is electrically connected with the first node of the first start-stage, and

wherein the first node setting transistor of the first start-stage has a first electrode which is electrically connected with the first node of the first start-stage, a second electrode which is electrically connected with the second clock signal line, a gate electrode which is electrically connected with the start signal line.

2. The display device according to claim 1 , wherein

the first start-stage includes a reset transistor,

the reset transistor has a gate electrode which is electrically connected with the first clock signal line and a first electrode which is electrically connected with the first node of the first start-stage, and a second electrode which is electrically connected with a low level voltage line.

3. The display device according to claim 1 , wherein

the first start-stage includes a low level voltage output transistor and a second node,

the low level voltage output transistor has a gate electrode which is electrically connected with a second node, a first electrode which is electrically connected with the first electrode of the output transistor of the first start-stage, and a second electrode which is electrically connected with a low level voltage line.

4. A shift register circuit comprising:

a plurality of cascaded stages including a first start-stage, a second start-stage and M stages (M is natural number equal to or greater than 2);

a start signal line electrically connected with the first start-stage and the second start-stage;

a plurality of output signal lines electrically connected with M stages respectively for applying a conducting potential which makes a pixel transistor electrically connecting with the output signal line conductive;

a first clock signal line electrically connected with the plurality of cascaded stages and applying a first clock signal;

a second clock signal line electrically connected with the plurality of cascaded stages and applying a second clock signal,

a third clock signal line electrically connected with the plurality of cascaded stages and applying a third clock signal,

a fourth clock signal line electrically connected with the plurality of cascaded stages and applying a fourth clock signal,

an output signal line of the first start-stage configured to apply the conducting potential to a first stage of M stages;

an output signal line of the second start-stage configured to apply the conducting potential to a Mth stage of M stages;

wherein the first clock, the second clock, the third clock, and the fourth clock become the conducting potential in order when forward direction scanning,

wherein the fourth clock, the third clock, the second clock, and the first clock become the conducting potential in order when reverse direction scanning,

wherein M stages, the first start-stage, and the second start-stage include an output transistor, a first node and a first node setting transistor,

wherein the output transistor of the first stage of M stages has a first electrode which is electrically connected with the output signal line, a second electrode which is electrically connected with the first clock signal line, and a gate electrode which is electrically connected with the first node of the first stage of M stages,

wherein the first node setting transistor of the first stage of M stages has a first electrode which is electrically connected with the first node of the first stage of the M stages, a second electrode and gate electrode which are electrically connected with the first electrode of the output transistor of the first start-stage,

wherein the output transistor of the Mth stage of M stages has a first electrode which is electrically connected with the output signal line, a second electrode which is electrically connected with the fourth clock signal line, and a gate electrode which is electrically connected with the first node of the Mth stage of M stages,

wherein the first node setting transistor of the Mth stage of M stages has a first electrode which is electrically connected with the first node of the Mth stage of M stages, a second electrode and gate electrode which are electrically connected with the first electrode of the output transistor of the second start-stage,

wherein the output transistor of the first start-stage has a first electrode which is electrically connected with the second electrode of the first node setting transistor of a first stage of M stages, a second electrode which is electrically connected with the third clock signal line, a gate electrode which is electrically connected with the first node of the first start-stage,

wherein the first node setting transistor of the first start-stage has a first electrode which is electrically connected with the first node of the first start-stage, a second electrode which is electrically connected with the second clock signal line, a gate electrode which is electrically connected with the start signal line,

wherein the output transistor of the second start-stage has a first electrode which is electrically connected with the second electrode of the first node setting transistor of the Mth stage of the M stages, a second electrode which is electrically connected with the second clock signal line, a gate electrode which is electrically connected with the first node of the second start-stage, and

wherein the first node setting transistor of the second start-stage has a first electrode which is electrically connected with the first node of the second start-stage, a second electrode which is electrically connected with the third clock signal line, a gate electrode which is electrically connected with the start signal line.

5. The display device according to claim 4 , wherein

the first start-stage includes a reset transistor,

the reset transistor has a gate electrode which is electrically connected with the first clock signal line and a first electrode which is electrically connected with the first node of the first start-stage, and a second electrode which is electrically connected with a low level voltage line.

6. The display device according to claim 4 , wherein

the first start-stage includes a low level voltage output transistor and a second node,

the low level voltage output transistor has a gate electrode which is electrically connected with a second node, a first electrode which is electrically connected with the first electrode of the output transistor of the first start-stage, and a second electrode which is electrically connected with a low level voltage line.

7. The display device according to claim 4 , wherein

the second start-stage includes a reset transistor,

the reset transistor has a gate electrode which is electrically connected with the fourth clock signal line and a first electrode which is electrically connected with the first node of the first start-stage, and a second electrode which is electrically connected with a low level voltage line.

8. The display device according to claim 4 , wherein

the second start-stage includes a low level voltage output transistor and a second node,

the low level voltage output transistor has a gate electrode which is electrically connected with a second node, a first electrode which is electrically connected with the first electrode of the output transistor of the second start-stage, and a second electrode which is electrically connected with a low level voltage line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →