IP Library Granted Patent US 10,108,163
Granted Patent B2
US 10,108,163 · App. 14/616,109 · Granted Oct 23, 2018

Production management apparatus, production management method and recording medium

Inventors: Kensuke Takahashi (Yokkaichi Mie, JP); Katsumi Yamada (Yokkaichi Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G05B19/0426G05B19/41865G05B2219/2602G05B2219/31427G05B2219/32424Y02P90/20
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Quick Facts
Patent No.
US 10,108,163
App. No.
14/616,109
Granted
Oct 23, 2018
Kind
B2
Abstract

In one embodiment, a production management apparatus includes a flow obtaining module configured to obtain a plurality of processing flows to process a wafer from a flow storage module. The apparatus further includes a route creating module configured to select a plurality of steps from the plurality of processing flows, and configured to create a processing route to execute the plurality of steps selected from the plurality of processing flows. The apparatus further includes a flow creating module configured to select a plurality of steps from the processing route, and configured to create a new processing flow including the plurality of steps selected from the processing route.

Claims (22)

1. A production management apparatus comprising:

a display; and

a computer which executes a program to perform operations including:

displaying, on the display, an edit screen to edit first to Nth processing flows for simultaneously processing a group of first to Nth wafers, where N is an integer of two or more, wherein the edit screen includes first to Nth editing areas which respectively and simultaneously display, in an editable manner, steps of the first to Nth processing flows for respectively processing the first to Nth wafers, wherein the steps of the first to Nth processing flows are displayed so as to be grouped together in respective stages, wherein each stage crosses the first to Nth editing areas, and each stage includes one step from each of the first to Nth processing flows such that a kth stage includes a kth step of each of the first to Nth processing flows displayed in the respective first to Nth editing areas;

setting, in response to a first type of user input, steps among the steps of the first to Nth processing flows, as common steps, wherein each common step is a step that is simultaneously applied to multiple of the first to Nth wafers, wherein common steps of a same type and which are to be applied simultaneously to the multiple of the first to Nth wafers are displayed together in a same stage across the first to Nth editing areas;

performing, in response to a second type of user input, an editing operation of replacing at least one of the common steps with a dummy step in at least one of the first to Nth processing flows, and displaying the dummy step in place of the common step in the corresponding editing area and in the corresponding stage to which the replaced common step belongs, wherein the common step that is applied in the corresponding stage to other wafers among the first to Nth wafers is not applied to the wafer corresponding to the at least one of the first to Nth processing flows in which the dummy step has been set, wherein, upon completion of setting common steps and dummy steps, the computer displays the edit screen such that each stage includes, respectively, one of (i) no dummy steps and only common steps of a same type which are simultaneously applied to all of the first to Nth wafers in that stage, (ii) at least one dummy step and only one common step which is uniquely applied to one of the first to Nth wafers in said one of the first to Nth processing flows in which the common step is set, in that stage, and (iii) at least one dummy step and plural common steps of a same type which are simultaneously applied to multiple of the first to Nth wafers, excluding the wafer for which the dummy step has been set, in that stage, wherein a total number of the common steps and the dummy steps in each stage combined is equal to N, whereby each of the first to Nth processing flows are individually editable such that steps in the respective first to Nth processing flows can be uniquely set for the first to Nth wafers without using branches; and

registering the first to Nth processing flows edited on the edit screen in a database via a network, wherein the registering comprises registering information of the common steps with respect to the first to Nth wafers as a wafer group, and registering information of each dummy step with respect to a wafer to which the dummy step has been applied.

2. The apparatus of claim 1 , wherein the edit screen includes a common step editing area for editing the common steps.

3. A semiconductor device production system comprising:

the production management apparatus of claim 1 ; and

at least one semiconductor production apparatus which is configured to process the first to Nth wafers according to the steps of the first to Nth processing flows edited and registered by the production management apparatus to produce semiconductor devices,

wherein the at least one semiconductor production apparatus simultaneously processes wafers for which common steps of a same type have been set in a given stage.

4. A production management method, comprising:

displaying, on a display, an edit screen to edit first to Nth processing flows for simultaneously processing a group of first to Nth wafers, where N is an integer of two or more, wherein the edit screen includes first to Nth editing areas which respectively and simultaneously display, in an editable manner, steps of the first to Nth processing flows for respectively processing the first to Nth wafers, wherein the steps of the first to Nth processing flows are displayed so as to be grouped together in respective stages, wherein each stage crosses the first to Nth editing areas, and each stage includes one step from each of the first to Nth processing flows such that a kth stage includes a kth step of each of the first to Nth processing flows displayed in the respective first to Nth editing areas;

setting, in response to a first type of user input, steps among the steps of the first to Nth processing flows, as common steps, wherein each common step is a step that is simultaneously applied to multiple of the first to Nth wafers, wherein common steps of a same type and which are to be applied simultaneously to the multiple of the first to Nth wafers are displayed together in a same stage across the first to Nth editing areas;

performing, in response to a second type of user input, an editing operation of replacing at least one of the common steps with a dummy step in at least one of the first to Nth processing flows, and displaying the dummy step in place of the common step in the corresponding editing area and in the corresponding stage to which the replaced common step belongs, wherein the common step that is applied in the corresponding stage to other wafers among the first to Nth wafers is not applied to the wafer corresponding to the at least one of the first to Nth processing flows in which the dummy step has been set, wherein, upon completion of setting common steps and dummy steps, the edit screen is displayed such that each stage includes, respectively, one of (i) no dummy steps and only common steps of a same type which are simultaneously applied to all of the first to Nth wafers in that stage, (ii) at least one dummy step and only one common step which is uniquely applied to one of the first to Nth wafers in said one of the first to Nth processing flows in which the common step is set, in that stage, and (iii) at least one dummy step and plural common steps of a same type which are simultaneously applied to multiple of the first to Nth wafers, excluding the wafer for which the dummy step has been set, in that stage, wherein a total number of the common steps and the dummy steps in each stage combined is equal to N, whereby each of the first to Nth processing flows are individually editable such that steps in the respective first to Nth processing flows can be uniquely set for the first to Nth wafers without using branches; and

registering the first to Nth processing flows edited on the edit screen in a database via a network, wherein the registering comprises registering information of the common steps with respect to the first to Nth wafers as a wafer group, and registering information of each dummy step with respect to a wafer to which the dummy step has been applied.

5. A non-transitory computer-readable recording medium containing a program which causes a computer to perform operations comprising:

displaying, on a display, an edit screen to edit first to Nth processing flows for simultaneously processing a group of first to Nth wafers, where N is an integer of two or more, wherein the edit screen includes first to Nth editing areas which respectively and simultaneously display, in an editable manner, steps of the first to Nth processing flows for respectively processing the first to Nth wafers, wherein the steps of the first to Nth processing flows are displayed so as to be grouped together in respective stages, wherein each stage crosses the first to Nth editing areas, and each stage includes one step from each of the first to Nth processing flows such that a kth stage includes a kth step of each of the first to Nth processing flows displayed in the respective first to Nth editing areas;

setting, in response to a first type of user input, steps among the steps of the first to Nth processing flows, as common steps, wherein each common step is a step that is simultaneously applied to multiple of the first to Nth wafers, wherein common steps of a same type and which are to be applied simultaneously to the multiple of the first to Nth wafers are displayed together in a same stage across the first to Nth editing areas;

performing, in response to a second type of user input, an editing operation of replacing at least one of the common steps with a dummy step in at least one of the first to Nth processing flows, and displaying the dummy step in place of the common step in the corresponding editing area and in the corresponding stage to which the replaced common step belongs, wherein the common step that is applied in the corresponding stage to other wafers among the first to Nth wafers is not applied to the wafer corresponding to the at least one of the first to Nth processing flows in which the dummy step has been set, wherein, upon completion of setting common steps and dummy steps, the computer displays the edit screen such that each stage includes, respectively, one of (i) no dummy steps and only common steps of a same type which are simultaneously applied to all of the first to Nth wafers in that stage, (ii) at least one dummy step and only one common step which is uniquely applied to one of the first to Nth wafers in said one of the first to Nth processing flows in which the common step is set, in that stage, and (iii) at least one dummy step and plural common steps of a same type which are simultaneously applied to multiple of the first to Nth wafers, excluding the wafer for which the dummy step has been set, in that stage, wherein a total number of the common steps and the dummy steps in each stage combined is equal to N, whereby each of the first to Nth processing flows are individually editable such that steps in the respective first to Nth processing flows can be uniquely set for the first to Nth wafers without using branches; and

registering the first to Nth processing flows edited on the edit screen in a database via a network, wherein the registering comprises registering information of the common steps with respect to the first to Nth wafers as a wafer group, and registering information of each dummy step with respect to a wafer to which the dummy step has been applied.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 042846/0146 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2015
From: TAKAHASHI, KENSUKE; YAMADA, KATSUMI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034909/0182 →
Continuity (2)
Provisional Application 62046035 · Sep 4, 2014
Related Publication 20160070250A1 · Mar 10, 2016