EXTERNAL VIDEO LOCKING AND SYNCHRONIZATION DEVICE
This disclosure describes an external video locking and synchronization device ( 104 ) in communication with a video source ( 102 ) and a target device ( 106 ). The external video locking and synchronization device ( 104 ) provides a video receiver ( 202 ), a memory ( 208 ), and a locking and synchronization circuitry ( 204 ). The video receiver ( 202 ) receives a video signal from the video source ( 102 ). The video signal has one or more video frames, each being associated with clocking information and frame synchronization information. The memory ( 208 ) is in communication with the video receiver ( 202 ) and stores the clocking information and the frame synchronization information. The locking and synchronization circuitry ( 204 ) adjusts vertical frequency of the video signal by a predetermined value; and generates a synchronized video signal for the target device ( 106 ), where the synchronized video signal is locked into the video signal.
1 . An external video locking and synchronization device for video signals where the device is in communication with a video source and a target device, comprising:
a video receiver that receives the video signal from the video source, wherein the video signal comprises one or more video frames, each being associated with a clocking information and a frame synchronization information;
a memory in communication with said video receiver, wherein said memory stores said clocking information and said frame synchronization information; and
a locking and synchronization circuitry, configured to:
adjust vertical frequency of the video signal by a predetermined value; and
generate a synchronized video signal for the target device, wherein said synchronized video signal is locked into the video signal.
2 . The claim according to claim 1 , further comprising a transmitter receiving said synchronized video signal for transmission to said target device at a predetermined frame rate.
3 . The claim according to claim 2 , further comprising a clock circuitry generating a clock signal to adjust said vertical frequency of said synchronized video signal based on said clocking information and said frame synchronization information associated with each video frame.
4 . The claim according to claim 1 , wherein said locking and synchronization circuitry is at least one of a field programmable gate array, an erasable programmable logic device, and a system-on-a-chip.
5 . The claim according to claim 1 , wherein the video signal is a high definition multimedia interface (HDMI) signal.
6 . A method to make an external video locking and synchronization device for video signals where the device is in communication with a video source and a target device, comprising:
providing a video receiver that receives the video signal from the video source, wherein the video signal comprises one or more video frames, each being associated with a clocking information and a frame synchronization information;
providing a memory in communication with said video receiver, wherein said memory stores said clocking information and said frame synchronization information; and
providing a locking and synchronization circuitry, configured to:
adjust vertical frequency of the video signal by a predetermined value; and
generate a synchronized video signal for the target device, wherein said synchronized video signal is locked into the video signal.
7 . The claim according to claim 6 , further comprising the step of providing a transmitter for receiving said synchronized video signal for transmission to said target device at a predetermined frame rate.
8 . The claim according to claim 7 , further comprising the step of providing a clock circuitry for generating a clock signal to adjust said vertical frequency of said synchronized video signal based on said clocking information and said frame synchronization information associated with each video frame.
9 . The claim according to claim 6 , wherein said locking and synchronization circuitry is at least one of a field programmable gate array, an erasable programmable logic device, and a system-on-a-chip.
10 . The claim according to claim 6 , wherein the video signal is a high definition multimedia interface (HDMI) signal.
11 . A method to use an external video locking and synchronization device for video signals where the device is in communication with a video source and a target device, comprising:
receiving the video signal with a video receiver from the video source, wherein the video signal comprises one or more video frames, each being associated with clocking information and frame synchronization information;
storing said clocking information and said frame synchronization information with a memory, said memory being in communication with said video receiver;
adjusting vertical frequency of the video signal by a predetermined value with a locking and synchronization circuitry; and
generating a synchronized video signal for the target device with said locking and synchronization circuitry, wherein said synchronized video signal is locked into the video signal.
12 . The claim according to claim 11 , further comprising the step of receiving said synchronized video signal with a transmitter for transmission to said target device at a predetermined frame rate.
13 . The claim according to claim 12 , further comprising the step of generating a clock signal with a clock circuitry to adjust said vertical frequency of said synchronized video signal based on said clocking information and said frame synchronization information associated with each video frame.
14 . The claim according to claim 11 , wherein said locking and synchronization circuitry is at least one of a field programmable gate array, an erasable programmable logic device, and a system-on-a-chip.
15 . The claim according to claim 11 , wherein the video signal is a high definition multimedia interface (HDMI) signal.
16 . A non-transitory program storage device readable by a computing device that tangibly embodies a program of instructions executable by said computing device to perform a method to use an external video locking and synchronization device for video signals where the device is in communication with a video source and a target device, comprising:
receiving the video signal with a video receiver from the video source, wherein the video signal comprises one or more video frames, each being associated with clocking information and frame synchronization information;
storing said clocking information and said frame synchronization information with a memory, said memory being in communication with said video receiver;
adjusting vertical frequency of the video signal by a predetermined value with a locking and synchronization circuitry; and
generating a synchronized video signal for the target device with said locking and synchronization circuitry, wherein said synchronized video signal is locked into the video signal.
17 . The claim according to claim 16 , further comprising the step of receiving said synchronized video signal with a transmitter for transmission to said target device at a predetermined frame rate.
18 . The claim according to claim 17 , further comprising the step of generating a clock signal with a clock circuitry to adjust said vertical frequency of said synchronized video signal based on said clocking information and said frame synchronization information associated with each video frame.
19 . The claim according to claim 16 , wherein said locking and synchronization circuitry is at least one of a field programmable gate array, an erasable programmable logic device, and a system-on-a-chip.
20 . The claim according to claim 16 , wherein the video signal is a high definition multimedia interface (HDMI) signal.